Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-24 are presented for examination.
Title
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
4. Claims 8 and 10 recite the limitation “the memory controller” in lines 2 and 3-4, respectively. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Nose et al. US Pub. No. 20220208270.
As per claims 1, 6-7, 11, and 21-23, Fig. 6A of Nose is directed to a memory device, comprising: a memory block (220, par. 65, Fig. 6A) including a plurality of string groups (50, Fig. 4B) connected to a plurality of word lines (WL0-WLn) ; an operation processor (500, par. 84, Fig. 13) configured to set a program operation mode of the memory block to one of a single-level cell (SLC) mode (binary mode, par. 86, Fig. 19) and a multi- level cell (MLC) mode (MLC mode, par. 86, Fig. 19) in response to a command received externally from the memory device (Fig. 12A); and an address allocator (Fig. 19) configured to allocate a row address of the memory block differently depending on the program operation mode (par. 86).
As per claims 2 and 12, a paragraph 64 of Nose discloses wherein the memory block stores 1 bit per unit memory cell in the SLC mode, and stores 2 or more bits per unit memory cell in the MLC mode.
As per claims 3, 13, paragraphs 37, 39 or 96 and 86 of Nose discloses wherein the address allocator allocates the row address so that the program operation is performed on a string group (two or more strings) basis in the SLC mode (37, 39 or 96) and is performed on a word line basis in the MLC mode (par. 86).
As per claims 4 and 14, Fig. 19 of Nose discloses wherein the address allocator allocates the row addresses based on the word line basis in the MLC mode by sequentially assigning the row addresses, respectively, to locations where string groups intersect with a target word line.
As per claims 5 and 15, Fig. 19 of Nose discloses wherein the address allocator allocates the row addresses based on the string group basis in the SLC mode by sequentially assigning the row addresses, respectively, to locations where word lines intersect with a target string group.
As per claims 8 and 18, a paragraph 86 and Figs. 19 and 20 of Nose disclose wherein the program order based on the row address is equally set by the memory controller in the SLC mode and the MLC mode, respectively.
As per claims 9 and 19, Figs. 4A and 4B of Nose discloses wherein: a first string group (220) among the plurality of string groups comprises first strings sharing a first drain select line (32 or 44, par. 61), each of the first strings comprises a drain select transistor (S2, Fig. 4A) connected to the first drain select line, memory cells connected to the plurality of word lines (30), and a source select transistor (S1) connected to a first source select line (32), a second string group (another 220, Fig. 4B) among the plurality of string groups comprises second strings sharing a second drain select line (44, par. 61), and each of the second strings comprises a drain select transistor (S2) connected to the second drain select line, memory cells connected to the plurality of word lines, and a source select transistor (S1) connected to a second source select line.
As per claims 10, 20, and 24 Fig. 4B and a paragraph 64 of Nose disclose wherein the operation processor erases a string group selected from among the plurality of string groups in response to a partial erase command received from the memory controller.
8. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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