DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al (CN 106027011) in view of Fujimoto (US 2019/0198620).
For claim 1, Zhu teaches a semiconductor device comprising:
a transistor (Q1), the transistor including a first electrode (top terminal of Q1) and a second electrode (bottom terminal of Q1);
a detector (Cd, Rd) configured to detect a voltage of the first electrode or a current flowing from the first electrode to the second electrode (iD) in a state where the voltage of the first electrode is a positive voltage higher than a voltage of the second electrode (an overcurrent state, see citation 1 below);
a comparison circuit (hysteresis comparator, AND gate, D flip flop) configured to compare a measurement value measured by the detector with a first threshold in the state (voltage corresponding to ID(max), see citation 2 below); and
a gate driver circuit (M1, M4, M5, AND2, NAND2, R2) configured to apply a first positive voltage higher than a threshold voltage of the transistor to the gate electrode in the state (VCC via M4 and R2), and apply a first negative voltage to the gate electrode (VEE via M5 and R2) when the measurement value exceeds the first threshold as a result of comparison in the comparison circuit (as understood by examination of Figures 2-3 and by citations 2-3 below).
Due to a lack of paragraph numbers in the translation, the following citations have been highlighted in the attached copy.
Zhu teaches:
Citation 1: “The overcurrent detecting circuit is composed of a detecting capacitor Cd and a charging resistor Rd, and the voltage on the detecting capacitor Cd can be expressed as: vo=iD
L
s
e
x
t
R
d
C
d
“.
Citation 2: “In Figure 3, vDS is the drain-source voltage of the SiC MOSFET, iD is the drain current, vprot is the protection voltage signal output by the logic control circuit, and vo is the voltage signal on the detection capacitor Cd. Voff(th) is the threshold voltage value set in advance. At time t0, the drain current rises, and vo detects a voltage signal with an increased amplitude. At time t1, the magnitude of the voltage signal exceeds the threshold voltage value set in advance, and the detection is performed. The drain current that has reached exceeds the safe range ID (max), and at time t2, the output voltage vprot of the logic control signal Q starts to rise, and at time t3, the gate-source voltage of the SiC MOSFET is clamped.”
Citation 3: “Vcc and Vee are positive and negative pressures for driving, respectively.”
Zhu fails to teach:
the transistor including a first electrode, a second electrode, an n-type first semiconductor region provided between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region provided between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region provided between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region.
It is noted that Zhu teaches that Q1 is a SiC MOSFET (see Technical Field) but fails to teach the details of the SiC MOSFET.
However, Fujimoto teaches a SiC MOSFET ([28] and Figure 8) including a first electrode (source 10), a second electrode (drain 11) an n-type first semiconductor region provided between the first electrode and the second electrode (2) and electrically connected to the second electrode (as understood by examination of Figure 8), a p-type second semiconductor region (3, 6) provided between the first semiconductor region and the first electrode and electrically connected to the first electrode (as understood by examination of Figure 8), an n-type third semiconductor region (5) provided between the second semiconductor region and the first electrode and electrically connected to the first electrode (as understood by examination of Figure 8), and a gate electrode facing the second semiconductor region (9, as understood by examination of Figure 8).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Fujimoto’s SiC MOSFET (Figure 8) to implement the Zhu’s SiC MOSFET (Q1) since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that a generic teaching of a SiC MOSFET suggests that any well-known SiC MOSFET can/should be used to implement this generic teaching.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill before the effective filing date of the invention.
For claim 2, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 1 and Fujimoto further teaches:
the first electrode contacts the first semiconductor region (via 3 and 6, as understood by examination of Figure 8).
For claim 3, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 2 and Fujimoto further teaches:
the contact between the first electrode and the first semiconductor region is Schottky contact (when an SBD is implemented as discussed in [31]).
For claim 4, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 1 and Zhu further teaches:
when the first negative voltage is applied to the gate electrode, the second semiconductor region facing the gate electrode is in an accumulation state (as understood by examination of Figures 2-3).
For claim 5, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 1 and Zhu further teaches:
wherein after applying the first negative voltage to the gate electrode, in the state, the comparison circuit compares the measurement value measured by the detector with a second threshold (Voff(th), see citation 2 above), and
in the state, when the measurement value falls below the second threshold in the comparison circuit, the gate driver circuit applies a second positive voltage higher than the threshold voltage to the gate electrode (as understood by examination of Figures 2-3).
For claim 6, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 5 and further teaches:
wherein when the detector detects the voltage of the first electrode, the second threshold is a voltage lower than the first threshold (see rejections of claims 1 and 5 above).
For claim 7, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 1 and further teaches:
wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are silicon carbide (as discussed in the rejection of claim 1 above).
For claim 12, Zhu teaches a method (Figures 2-3) of controlling a semiconductor device including a transistor (Q1), the method comprising:
applying a positive voltage higher than a voltage of the second electrode (bottom terminal of Q1) to the first (top terminal of Q1) electrode (an overcurrent state, see citation 1 below);
applying a first positive voltage higher than a threshold voltage of the transistor to the gate electrode (VCC, as understood by examination of Figure 2);
detecting a voltage of the first electrode or a current (iD) flowing from the first electrode to the second electrode (via Cd and Rd, see citation 1 below); and
comparing a detected measurement value (input to hysteresis comparator) with a first threshold (voltage corresponding to ID(max), see citation 2 below), and applying a first negative voltage to the gate electrode (VEE) when the measurement value exceeds the first threshold ((as understood by examination of Figures 2-3 and by citations 2-3 below).
Due to a lack of paragraph numbers in the translation, the following citations have been highlighted in the attached copy.
Zhu teaches:
Citation 1: “The overcurrent detecting circuit is composed of a detecting capacitor Cd and a charging resistor Rd, and the voltage on the detecting capacitor Cd can be expressed as: vo=iD
L
s
e
x
t
R
d
C
d
“;
Citation 2: “In Figure 3, vDS is the drain-source voltage of the SiC MOSFET, iD is the drain current, vprot is the protection voltage signal output by the logic control circuit, and vo is the voltage signal on the detection capacitor Cd. Voff(th) is the threshold voltage value set in advance. At time t0, the drain current rises, and vo detects a voltage signal with an increased amplitude. At time t1, the magnitude of the voltage signal exceeds the threshold voltage value set in advance, and the detection is performed. The drain current that has reached exceeds the safe range ID (max), and at time t2, the output voltage vprot of the logic control signal Q starts to rise, and at time t3, the gate-source voltage of the SiC MOSFET is clamped.”
Citation 3: “Vcc and Vee are positive and negative pressures for driving, respectively.”
Zhu fails to teach:
the transistor including a first electrode, a second electrode, an n-type first semiconductor region provided between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region provided between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region provided between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region.
However, Fujimoto teaches a SiC MOSFET ([28] and Figure 8) including a first electrode (source 10), a second electrode (drain 11) an n-type first semiconductor region provided between the first electrode and the second electrode (2) and electrically connected to the second electrode (as understood by examination of Figure 8), a p-type second semiconductor region (3, 6) provided between the first semiconductor region and the first electrode and electrically connected to the first electrode (as understood by examination of Figure 8), an n-type third semiconductor region (5) provided between the second semiconductor region and the first electrode and electrically connected to the first electrode (as understood by examination of Figure 8), and a gate electrode facing the second semiconductor region (9, as understood by examination of Figure 8).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Fujimoto’s SiC MOSFET (Figure 8) to implement the Zhu’s SiC MOSFET (Q1) since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that a generic teaching of a SiC MOSFET suggests that any well-known SiC MOSFET can/should be used to implement this generic teaching.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill before the effective filing date of the invention.
For claim 13, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 12 and Fujimoto further teaches:
the first electrode contacts the first semiconductor region (via 3 and 6, as understood by examination of Figure 8).
For claim 14, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 13 and Fujimoto further teaches:
the contact between the first electrode and the first semiconductor region is Schottky contact (when an SBD is implemented as discussed in [31]).
For claim 15, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 12 and Zhu further teaches:
when the first negative voltage is applied to the gate electrode, the second semiconductor region facing the gate electrode is in an accumulation state (as understood by examination of Figures 2-3).
For claim 16, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 12 and Zhu further teaches:
wherein after applying the first negative voltage to the gate electrode, in the state, the comparison circuit compares the measurement value measured by the detector with a second threshold (Voff(th), see citation 2 above), and
in the state, when the measurement value falls below the second threshold in the comparison circuit, the gate driver circuit applies a second positive voltage higher than the threshold voltage to the gate electrode (as understood by examination of Figures 2-3).
For claim 17, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 16 and further teaches:
wherein when the detector detects the voltage of the first electrode, the second threshold is a voltage lower than the first threshold (see rejections of claims 12 and 16 above).
For claim 18, the combination of Zhu and Fujimoto as cited above teaches the limitations of claim 1 and further teaches:
wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are silicon carbide (as discussed in the rejection of claim 12 above).
Claim(s) 8-11 and 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and Fujimoto.
For claims 8-11 and 19-22, the combination of Zhu and Fujimoto as cited above teaches the limitations of claims 1 and 12 respectively but fails to teach the specific values and ranges as claimed.
However, the claimed relationships can easily be set by selecting specific component values for Zhu’s Figure 2. Since the component values can be set to any values desired (so long as they do not depart from the intended operation), creating the claimed relationships would only involve routine “design optimization” which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation).
Also, note MPEP 2144.05-II-A and 2144.05-III-A which state:
In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Applicants can rebut a prima facie case of obviousness by showing the criticality of the range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)…+
… In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946) (“Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies.”)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Michael et al (US 2014/0034963) teaches a SiC transistor relevant to Applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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