Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 01/07/2025 has been entered. Claims 1, 6, and 17 have been amended. Claim 2 has been canceled. Claims 1 and 3-20 remain pending in the application. Rejections of claims 6 under 35 U.S.C. 112(a) (pre-AIA 35 U. S. C. 112, first paragraph) are withdrawn.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 3-6, and 8-11 are rejected under 35 U.S.C. 103 as unpatentable over CHO (US 20220285647 A1) in view of KIM (US 20180061894 A1).
Regarding claim 1, CHO (Figs. 1, 4-5, and 7-10) discloses a display apparatus, comprising:
a first glass substrate (glass substrate 100; [0090]) having a display area and a non-display area adjacent to the display area (display area DA and non-display area NA);
a buffer layer (buffer layer 101) disposed on the first glass substrate (substrate 100) and extending from the display area to the non-display area (e.g., Figs. 4-5 and 7-10; display area DA and non-display area NA);
a gate insulating layer (gate insulating layer 103), an interlayer insulating layer (insulating layer 105), a protective layer (insulation layer 107), and a thin film transistor (TFT T1) provided on the buffer layer (buffer layer 101), the thin film transistor (TFT T1) comprising an active layer formed of an oxide semiconductor material (semiconductor layer A1; [0093]), a gate electrode, a source electrode, and a drain electrode (TFT T1 comprising a gate electrode G1, a source electrode S1, and a drain electrode D1);
a first planarization layer (first planarization layer 109) formed on the thin film transistor (TFT T1);
a first electrode (electrode 310) connected to the thin film transistor (TFT T1) through a contact hole formed in the first planarization layer (contact hole formed in first planarization layer 109);
an organic light emitting layer provided on the first electrode, the organic light emitting layer comprising a plurality of emitting layer stack (organic light emitting layer 320 comprising a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, an electron injection layer; [0114]);
a cathode electrode (cathode 330) disposed on the display area and non-display area (display area DA and non-display area NA) and covering the organic light emitting layer (organic light emitting layer 320) and the first electrode (electrode 310);
an encapsulation layer (encapsulation layer 400) formed on the cathode electrode (cathode 330) and comprising at least two inorganic layers (encapsulation layer 400 comprising a first inorganic encapsulation layer 410 and a second inorganic encapsulation layer 430; [0121]);
at least one dam (dam 120) surrounding the display area (display area DA) and disposed on the non-display area (non-display area NA); and
a plurality of second planarization layers (second planarization layers 111) disposed on the non-display area (non-display area NA) and located between the dam (dam 120) and display area (display area DA);
wherein the non-display area (non-display area NA) includes a plurality of the first electrodes (electrodes 310a; [0131]),
wherein each of the plurality of first electrodes (electrodes 310a) is disposed between each of the plurality of second planarization layers (second planarization layers 111) and the encapsulation layer (encapsulation layer 400), and
wherein the plurality of first electrodes (electrodes 310a) are spaced apart from each other (e.g., Figs. 4-5 and 7-10).
QU does not disclose a second substrate having a color filter layer and a filling member disposed between the encapsulation layer and second substrate. However, the above features are well known in display device. As a reference, KIM (Figs. 5 and 7-8) discloses a display device similar to that disclosed by CHO, comprising: a second substrate (substrate 112) disposed on the first glass substrate (glass substrate 111) and having a color filter layer (color filter layer comprising color filters 291, 292, and 293); and an encapsulation layer (encapsulation layer 280) comprising at least two inorganic layers (inorganic layer 281 and inorganic layer 283; [0122]), and a filling member (member 320) disposed between the encapsulation layer (encapsulation layer 280) and the color filter layer (color filter layer comprising color filters 291, 292, and 293). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM to the display device of CHO. The combination/motivation would be to provide a full color OLED display device.
Regarding claim 3 CHO in view of KIM discloses the display apparatus of claim 1, CHO (Figs. 1, 4-5, and 7-10) discloses wherein widths of the plurality of second planarization layers are different from each other, or heights of the plurality of second planarization layers are different from each other (Figs. 4-5 and 7-10; planarization layers 111).
Regarding claim 4, CHO in view of KIM discloses the display apparatus of claim 1, CHO (Figs. 1, 4-5, and 7-10) discloses further comprising a third planarization layer (planarization layer 109b/111b) adjacent to the at least one dam (dam 120).
Regarding claim 5, CHO in view of KIM discloses the display apparatus of claim 4, CHO (Figs. 1, 4-5, and 7-10) discloses wherein the first planarization layer (first planarization layer 109), the second planarization layer (second planarization layer 111), and the third planarization layer (third planarization layer 109b) include a same material ([0106]-[0107]).
Regarding claim 6, CHO in view of KIM discloses the display apparatus of claim 4, wherein the third planarization layer (third planarization layer 109b) is disposed on the second substrate (substrate 112) and includes a same material ([0106]-[0107]) as the second planarization layer (second planarization layer 111).
Regarding claim 8, CHO in view of KIM discloses the display apparatus of claim 1, CHO (Figs. 1, 4-5, and 7-10) discloses wherein the first electrode (anode electrode 310) includes Ag and Al ([0111]; Ag and Al).
Regarding claim 9, CHO in view of KIM discloses the display apparatus of claim 1, CHO (Figs. 1, 4-5, and 7-10) discloses wherein the encapsulation layer (encapsulation layer 400) covers the plurality of second planarization layers (planarization layers 111).
Regarding claim 10, CHO in view of KIM discloses the display apparatus of claim 1, CHO (Figs. 1, 4-5, and 7-10) discloses further comprising a transparent connection member (transparent connection member 420) disposed in the non-display area (non-display area NDA), wherein each of the encapsulation layer (encapsulation layer comprising a first inorganic encapsulation layer 410 and a second inorganic encapsulation layer 430) and the transparent connection member (transparent connection member 420) is partially disposed between the plurality of second planarization layers (planarization layers 111).
Regarding claim 11, CHO in view of KIM discloses the display apparatus of claim 4, KIM (Figs. 5 and 7-8) discloses wherein the color filter layer (color filter layer comprising color filters 291, 292, and 293) faces the corresponding first electrode (anode electrode 261).
5. Claim 7 is rejected under 35 U.S.C. 103 as unpatentable over CHO (US 20220285647 A1) in view of KIM (US 20180061894 A1) and further in view of QU (US 20230232661 A1).
Regarding claim 7, CHO in view of KIM discloses the display apparatus of claim 1, but does not disclose wherein the plurality of light emitting layer stacks have a plurality of green light emitting layers. However, QU (Figs. 1-2, 5, and 8-9) discloses a display device similar to that disclosed by CHO and KIM, wherein the plurality of light emitting layer stacks have a plurality of green light emitting layers (green light emitting layer 25G; Fig. 1 and [0037] and [0041]-[0042]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from QU to the display device of CHO in view of KIM. The combination/motivation would be to provide a full color OLED display device.
6. Claims 12-13 and 15 are rejected under 35 U.S.C. 103 as unpatentable over CHO (US 20220285647 A1) in view of KIM (US 20180061894 A1) and further in view of HEE (KR 102649202 B1) or ZOU (US 20210408474 A1).
Regarding claim 12, CHO in view of KIM discloses the display apparatus of claim 1, but does not disclose an undercut portion as claimed. However, HEE discloses a display apparatus, further comprising an undercut portion (e.g., Figs. 1 and 3; undercut portion) disposed between the first glass substrate (glass substrate 100) and each of the plurality of second planarization layer (e.g., Figs. 1-2 and 3-4; planarization layers 713 or planarization layers 743), wherein the organic light emitting layer (e.g., Figs. 1 and 3; organic light emitting layer 520) extends to the non-display area, and the organic light emitting layer disposed in the non-display area (e.g., Figs. 1 and 3;non-display area NA) has a plurality of segments disconnected from each other by the undercut portion (e.g., Figs. 1 and 3; undercut portion). Similar to HEE, ZOU (e.g., Figs. 1 and 2) discloses the same features as claimed. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HEE or ZOU to the display device of CHO in view of KIM. The combination/motivation would be to provide an element arrangement in a non-display area of a display device.
Regarding claim 13, CHO in view of KIM and further in view of HEE or ZOU discloses the display apparatus of claim 12, HEE discloses further comprising a plurality of inorganic layers (e.g., Figs. 1-2 and 3-4; inorganic layers 711-712 or inorganic layers 741-742) disposed between the first glass substrate (glass substrate 100) and each of the plurality of second planarization layer (e.g., Figs. 1-2 and 3-4; planarization layers 713 or planarization layers 743), wherein the undercut portion (e.g., Figs. 1 and 3; undercut portion) is formed by removing at least a portion of the plurality of inorganic layers (e.g., Figs. 1-2 and 3-4; inorganic layers 711-712 or inorganic layers 741-742). Similar to HEE, ZOU (e.g., Figs. 1 and 2) discloses the same features as claimed. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from HEE or ZOU to the display device of CHO in view of KIM for the same reason above.
Regarding claim 15, CHO in view of KIM and further in view of HEE or ZOU discloses the display apparatus of claim 12, HEE discloses wherein the first glass substrate is (glass substrate 100) spaced apart from each of the plurality of second planarization layer (e.g., Figs. 1-2 and 3-4; planarization layers 713 or planarization layers 743) with the undercut portion interposed therebetween (e.g., Figs. 1 and 3; undercut portion).
Allowable Subject Matter
7. Claims 17-20 are allowed. Claims 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The reasons for allowance are referred to the Office action dated on 10/07/2025.
Response to Arguments
6. Regarding claim 1, applicant’s arguments have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In view of amendments, the reference of CHO (US 20220285647 A1) has been used for new ground rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623