Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the application filed on 02/10/2025, in which claims 1-20 are presented for the examination.
Drawings
The drawings filed on 02/10/2025 are accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim recites “ECS information” and “a quantity of the one or more refresh operations determined based on the ECS information” but fails to clearly define the structure or meaning of these items. It is unclear what constitutes ECS information and how the quantity of refresh operations is measured or determined. Accordingly, the metes and bounds of the claimed invention cannot be reasonable ascertained.
More particularly, “ECS information” is defined only as “based on a count of errors” but unclear whether it is a) raw count b) a rate (errors per time/cycle) c) a threshold? Thus, the term “ECS information” is vague and does not provide clear boundaries as to what structure or data is encompassed.
The term “Quantity of the one or more refresh operations” is unclear in terms of whether is it a) number of refresh commands b) frequency (rate) c) duration d) number of rows refreshed? It is unclear what constitutes the “quantity” of refresh operations and how it is measured.
The term “determined based on” is very broad and it does not provide indication of a) how determination is made b) any algorithm or rule is provided.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim recites “an error check and scrub (ECS) logic circuit configured to generate ECS information based on a count of errors in the memory array; and a refresh control circuit configured to perform one or more of refresh operations responsive to a refresh signal, wherein a quantity of the one or more refresh operations is determined based on the ECS information”.
The specification describes (See para. [0013]), generating ECS information, including count of codewords containing errors, an address, a count of a row having the most errors and other error related metrics. Thus, the specification provides support for generating ECS information.
However, the specification does not describe determining quantity of refresh operations based on the ECS information. In particular, the specification fails to disclose how ECS information is used to control or adjust refresh operation or any relationship between error metrics and refresh behavior. Accordingly, the specification does not convey possession of the claimed subject matter, specifically, the determination of a quantity of refresh operations based on ECS information.
For the examining purposes, examiner interprets ECS information as number of errors.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-11, 13-17, 20 are rejected under 35 U.S.C. 102(a)1(1) as being anticipated by Brittain et al. (US 2008/0072116, referred herein after Brittain).
As per claim 10, Brittain discloses an apparatus comprising:
a module logic circuit (Fig. 1, refresh logic 120, [0024]) configured to provide a refresh command (refresh logic 120 provides refresh rate adjustment command);
a plurality of memory devices configured to receive the refresh command in common (Fig. 1, memory devices 150), each of the plurality of memory devices comprising:
a register configured to store error correct and scrub (ECS) information (Fig. 2, [0027], an error record is added to error data store 240);
a refresh rate adjustment circuit configured to determine a quantity of refresh operations performed by the memory device responsive to the refresh command based on the ECS information (Fig. 1, refresh logic 120, memory controller executes refresh logic 120 to adjust the refresh rate (125) based on the number of bit errors encountered).
As per claim 11, Brittain discloses the apparatus of claim 10, wherein a first and a second of the plurality of memory devices perform different numbers of refresh operations responsive to the same refresh command ([0024], [0025], plurality of memory devices (different types of memory) perform different numbers off refresh cycles as claimed).
As per claim 13, Brittain discloses a method comprising:
performing error correct and scrub (ECS) operations to correct errors in a memory array of a memory device (Fig. 1, error analysis logic 110, [0023], [0013], the number of correctable errors that occur during a period of time are counted for a number of memory ranks that are included in the hardware memory);
generating ECS information based on a count of the corrected errors; and adjusting a refresh rate of the memory device based on the ECS information (Fig. 3, [0031], [0013], refresh rates for the individual memory ranks can be adjusted by comparing the error count associated with each of the memory ranks with a second set of thresholds that is used for individual memory ranks).
As per claim 14, Brittain discloses the method of claim 13, further comprising: updating the ECS information at the end of an ECS cycle (Fig. 2, step 250, [0028]); comparing the updated ECS information to previous ECS information from a previous ECS cycle; and adjusting the refresh rate based on the comparing (Fig. 3, 325, [0012], [0013], [0031], refresh rates for the individual memory ranks can be adjusted by comparing the error count associated with each of the memory ranks with a second set of thresholds that is used for individual memory ranks).
As per claim 15, Brittain discloses the method of claim 14, further comprising: finding a difference between the updated ECS information and the previous ECS information and adjusting the refresh rate based on the difference (Fig. 3, step 330, 340, 360, [0031], [0034], comparing the error count associated with each of the memory ranks with a second set of thresholds that is used for individual memory ranks, difference in error count is checked against the thresholds as claimed).
As per claim 16, Brittain discloses the method of claim 14, further comprising: comparing the difference to an upper threshold and increasing the refresh rate if the difference is above the upper threshold; comparing the difference to a lower threshold and decreasing the refresh rate if the difference is below the lower threshold; and keeping the refresh rate at a current level if the difference is between the upper threshold and the lower threshold ([0024], [0025], [0031], When increased numbers of bit errors are identified, refresh logic 120 increases the refresh rate…As bit errors decrease, refresh logic 120 decreases the refresh rate).
As per claim 17, Brittain discloses the method of claim 13, further comprising continuously monitoring the ECS information during ECS operations ([0030], [0009], computer continually monitors for errors as claimed).
As per claim 20, Brittain discloses the method of claim 13, further comprising adjusting the refresh rate by changing a quantity of refresh operations performed responsive to a refresh command (Fig. 3, step 350, [0029]-[0031], default refresh rate is used and based on error count, refresh rate is adjusted).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9, 12-13, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Brittain et al. (US 2008/0072116, referred herein after Brittain) in view of Yang (US 2015/0301888, referred herein after Yang).
As per claim 1, Brittain discloses an apparatus comprising:
an error check and scrub (ECS) logic circuit (Fig. 1, error analysis logic 110, [0023]) configured to generate ECS information based on a count of errors in the memory array; and ([0013], the number of correctable errors that occur during a period of time are counted for a number of memory ranks that are included in the hardware memory);
a refresh control circuit ([0024], refresh logic 120, Fig. 1) configured to perform one or more of refresh operations responsive to a refresh signal, wherein a quantity of the one or more refresh operations is determined based on the ECS information (Fig. 3, [0031], [0013], refresh rates for the individual memory ranks can be adjusted by comparing the error count associated with each of the memory ranks with a second set of thresholds that is used for individual memory ranks);
Brittain does not specifically disclose memory array;
However, Yang teaches memory array (Fig. 1, [0005], a flash memory stores data with memory unit arrays, and may be implemented with a floating-gate transistor);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Yang’s method for reading data stored in a flash memory into Brittain’s method for altering memory command stream to a hardware memory because one of the ordinary skill in the art would have been motivated to provide improved data retention and reduced power consumption.
As per claim 2, Brittain discloses the apparatus of claim 1, wherein the ECS logic circuit is configured to update the ECS information at the end of an ECS cycle (Fig. 2, step 250, [0028]), and
wherein the refresh control circuit is configured to compare the updated ECS information to previous ECS information and determine the quantity of the one or more refresh operations based on the comparison (Fig. 3, 325, [0012], [0013], [0031], refresh rates for the individual memory ranks can be adjusted by comparing the error count associated with each of the memory ranks with a second set of thresholds that is used for individual memory ranks).
As per claim 3, Brittain discloses the apparatus of claim 2, wherein the refresh control circuit is configured to compare a difference between the updated ECS information and the previous ECS information to an upper threshold and to a lower threshold, wherein the refresh control circuit is configured to determine the quantity based on the comparison (Fig. 3, step 330, 340, 360, [0031], [0034], comparing the error count associated with each of the memory ranks with a second set of thresholds that is used for individual memory ranks, difference in error count is checked against the thresholds as claimed).
As per claim 4, Brittain discloses the apparatus of claim 2, wherein the refresh control circuit includes a refresh rate adjustment circuit comprising: a latch configured to store the previous ECS information (Fig. 2, error data store 240 stores error information);
a comparator circuit configured to determine a difference between the updated ECS information and the previous ECS information (Fig. 3, step 325, [0031]), wherein the comparator is configured to provide a refresh rate adjustment signal based on the difference and wherein the number is adjusted based on the refresh rate adjustment signal (Fig. 3, steps 300-335, [0031], the refresh rate is set based upon the retrieved thresholds. the refresh rate that is set may be an increased refresh rate, a decreased refresh rate, or the same refresh rate when compared to the refresh rate that was previous set for the memory).
As per claim 5, Brittain discloses the apparatus of claim 1, wherein the ECS logic circuit is configured to update a selected one of a plurality of ECS information values ([0027], error record is updated into data store), each associated with a bank of the memory array, after performing a set of ECS operations on the respective bank, and wherein the refresh rate control circuit is configured to determine the quantity of the one or more refresh operations based on one of the plurality of ECS information values when the ECS information is updated (Fig. 2, step 280, Fig. 3, [0028]-[0029], refresh rate is adjusted based on error threshold (ie ECS information)).
As per claim 6, Brittain discloses the apparatus of claim 1, wherein the refresh rate control circuit is configured to continuously monitor the ECS information as it is updated ([0030], [0009], computer continually monitors for errors as claimed).
As per claim 8, Brittain discloses the apparatus of claim 1, wherein the refresh control circuit (Fig. 1, refresh logic) includes a baseline refresh rate (default refresh rate) which determines a base line quantity of refresh operations, and wherein the quantity is adjusted away from the base line number based on the ECS information (Fig. 3, step 350, [0029]-[0031], default refresh rate is used and based on error count, refresh rate is adjusted).
As per claim 9, Brittain does not specifically disclose the apparatus of claim 1, further comprising an error correction code (ECC) circuit configured to correct errors in a codeword, wherein the ECS information includes an ECS count, and wherein the ECS logic circuit is configured to cause a codeword to be read out to the ECC circuit, and wherein the ECS logic circuit is further configured to increment the ECS count responsive to the ECC circuit correcting an error in the codeword;
However, Yang discloses an error correction code (ECC) circuit configured to correct errors in a codeword, wherein the ECS information includes an ECS count, and wherein the ECS logic circuit is configured to cause a codeword to be read out to the ECC circuit, and wherein the ECS logic circuit is further configured to increment the ECS count responsive to the ECC circuit correcting an error in the codeword ([0034], [0050], [0051], the codeword error correction (ECC) operation performed upon the codeword read from the memory units);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Yang’s method for reading data stored in a flash memory into Brittain’s method for altering memory command stream to a hardware memory because one of the ordinary skill in the art would have been motivated to provide improved data retention and reduced power consumption.
As per claim 12, Brittain does not specifically disclose the apparatus of claim 10, wherein each of the plurality of memory devices further includes: a memory array configured to store a plurality of codewords; an error correct code (ECC) circuit configured to correct errors in a codeword as part of an ECS operation; an ECS logic circuit configured to perform ECS operations on each of the plurality of codewords and update the ECS information if an error was detected by the ECC circuit;
However, Yang discloses each of the plurality of memory devices further includes: a memory array (Fig. 1, [0005]) configured to store a plurality of codewords; an error correct code (ECC) circuit configured to correct errors in a codeword as part of an ECS operation; an ECS logic circuit configured to perform ECS operations on each of the plurality of codewords and update the ECS information if an error was detected by the ECC circuit ([0034], [0050], [0051], the codeword error correction (ECC) operation performed upon the codeword read from the memory units);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Yang’s method for reading data stored in a flash memory into Brittain’s method for altering memory command stream to a hardware memory because one of the ordinary skill in the art would have been motivated to provide improved data retention and reduced power consumption.
As per claim 19, Brittain does not specifically disclose the method of claim 13, further comprising performing the ECS operation by: reading a codeword from the memory array to an error correction code (ECC) circuit; correcting an error in the codeword with the ECC circuit; writing the corrected codeword back into the memory array; and updating the ECS information if an error was corrected;
However, Yang discloses performing the ECS operation by: reading a codeword from the memory array to an error correction code (ECC) circuit; correcting an error in the codeword with the ECC circuit; writing the corrected codeword back into the memory array; and updating the ECS information if an error was corrected ([0034], [0050], [0051], the codeword error correction (ECC) operation performed upon the codeword read from the memory units);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Yang’s method for reading data stored in a flash memory into Brittain’s method for altering memory command stream to a hardware memory because one of the ordinary skill in the art would have been motivated to provide improved data retention and reduced power consumption.
Claims 7, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Brittain and Yang in view of Richter et al. (US 2020/0192749, referred herein after Richter).
As per claim 7, neither Brittain nor Yang discloses the apparatus of claim 6, wherein the memory array includes a plurality of word lines wherein the ECS logic circuit configured to perform ECS operations on a word line by word line basis, and wherein the refresh rate control circuit is configured to determine an error rate based on the number of errors detected on the previous N word lines;
However, Richter discloses the memory array includes a plurality of word lines (Fig. 2, memory arrays include word lines 210), wherein the ECS logic circuit configured to perform ECS operations on a word line by word line basis, and wherein the refresh rate control circuit is configured to determine an error rate based on the number of errors detected on the previous N word lines (Fig. 3, the memory device 310 may have an error counter 340 determines the quantity of detected and/or corrected errors).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Richter’s method of dynamic control of error management into Yang’s method for reading data stored in a flash memory and Brittain’s method for altering memory command stream to a hardware memory because one of the ordinary skill in the art would have been motivated to improve error management, detection, correction, and reporting in a memory system.
As per claim 18, neither Brittain nor Yang discloses the method of claim 17, further comprising: performing ECS operations to detect errors along a word line on a word line-by-word line basis; updating a count of a number of errors detected by the ECS operations in the N most recent word lines; and adjusting the refresh rate based on the number of errors in the N most recent word lines;
However, Richter discloses performing ECS operations to detect errors along a word line on a word line-by-word line basis; updating a count of a number of errors detected by the ECS operations in the N most recent word lines; and adjusting the refresh rate based on the number of errors in the N most recent word lines (Fig. 3, the memory device 310 may have an error counter 340 determines the quantity of detected and/or corrected errors);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Richter’s method of dynamic control of error management into Yang’s method for reading data stored in a flash memory and Brittain’s method for altering memory command stream to a hardware memory because one of the ordinary skill in the art would have been motivated to improve error management, detection, correction, and reporting in a memory system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form 892.
Lovelace teaches a method to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM).
D’abreu teaches a device for selectively refreshing a region of a non-volatile memory of a data storage device.
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/KAMINI B PATEL/Primary Examiner, Art Unit 2114
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