Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant has amended their application as follows:
Amended: 1-4, 6-7, 12, 14-16 and 18
Cancelled: 13
Added: 23
Therefore, claims 1-12 and 14-23 are currently pending in the instant application.
Response to Arguments
Applicant's arguments filed 08/28/2026 have been fully considered but they are not persuasive. The claim amendments to claims 6 and 18 do not recite the full extent of the objected claim 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7, 10-11 and 18-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2016/0240128 A1, hereinafter “Kim”) in view of Hauck et al. (US Patent No. 6,091,426; hereinafter “Hauck”).
As to claim 6, Kim (Fig. 1) discloses an Image processing circuitry (100) comprising:
an image data line buffer (110) configured to store lines of image data corresponding to lines of display pixels of an electronic display (Para. 0060), wherein the lines of the image data (1st row, 2nd row..) comprise first pixel data corresponding to a first display pixel of the display pixels (Fig. 4 element left first row pixel), second pixel data corresponding to a second display pixel of the display pixels (left second row pixel), third pixel data corresponding to a third display pixel of the display pixels (second first row pixel), and fourth pixel data corresponding to a fourth display pixel of the display pixels (second second row pixel);
difference circuitry (130) configured to obtain two or more image data differences between the first pixel data, the second pixel data, the third pixel data, and the fourth pixel data of the image data associated with display pixels disposed in different lines (Fig. 5; Para. 0068, “The coupling voltage calculator can calculate the line coupling voltage Vc that occurs on the Mth data line 510 based on the difference between the grayscale data voltage Vc provided to the adjacent pixels Px coupled to the Mth data line 510”; the pixel would be based on different rows) and configured to be consecutively programmed via a shared data line (Para. 0068, data line 510); and
a pixel compensation lookup table (Fig. 1 element 150) configured to generate a pixel data adjustment corresponding to pixel data of the image data associated with a target display pixel based on the two or more scaled image data differences (Para. 0064, 0068, “the compensating data generator can generate the compensating data voltage Vdc that compensates the line coupling voltage Vc of each of the data lines DL”).
Kim does not disclose difference circuitry configured to obtain two or more scaled image data differences.
However, Hauck teaches difference circuitry configured to obtain two or more scaled image data differences (Fig. 4 element 50; Col. 6 lines 20-31, weighted coefficient would be applied to all pixels starting from the first pixel).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to apply scaling in the device disclosed by Kim. The motivation would have been to perform the smoothing operation (Hauck; Col. 6 lines 19-23).
As to claim 7, Kim discloses the image processing circuitry of claim 6, wherein the image data line buffer is configured to store N+1 lines of image data and the target display pixel is in a first line of the N+1 lines of image data in order of programming on the electronic display (Para. 0061, pixel value of first pixel).
As to claim 10, Kim discloses the image processing circuitry of claim 7, wherein the number N is greater than 2 (Fig. 4; Para. 0010-0011).
As to claim 11, Kim (Fig. 6) discloses the image processing circuitry of claim 6, comprising addition circuitry (250) configured to add the pixel data adjustment to the pixel data of the image data associated with the target display pixel before the pixel data of the image data associated with the target display pixel is programmed into the target display pixel (Para. 0064).
As to claim 18, Kim (Fig. 6) discloses an electronic device (200) comprising:
first processing circuitry configured to generate image data (Para. 0060, external device); and
second processing circuitry (220) configured to adjust, based on a sum of a first difference (Fig. 5 element Vd1) and a second difference (Vd2; Para. 0068, “ For example, the coupling voltage calculator calculates the amount of the coupling C(N) that occurs on the pixel in the Nth row of the Mth data line 510 by multiplying the coupling ratio Rc by the difference between the grayscale data voltage Vd(N−1) of the (N−1)th row and the grayscale data voltage Vd(N) of the Nth row”; “The coupling voltage calculator 130 can calculate amounts of the coupling that occurs on the pixels based on the difference between the grayscale data voltages Vd provided to the adjacent pixels coupled to the data line, and output the mean value of the amounts of the coupling as the line coupling voltage Vc”), adjust the image data to compensate for coupling (Vc) between display pixels and data lines of an electronic display (Para. 0068), wherein the first scaled difference to a difference between first pixel data and second pixel data scaled based on a separation between a first line and a second line (Para. 0068, first row and second row pixels), and wherein the second scaled difference corresponds to a difference between third pixel data and fourth pixel data scaled based on a separation between a third line and a fourth line (third row and fourth row pixels).
Kim does not disclose second processing circuitry configured to adjust, based on a sum of a first scaled difference and a second scaled difference.
However, Hauck teaches second processing circuitry configured to adjust, based on a sum of a first scaled difference (Fig. 5 element Vd1) and a second scaled difference (Fig. 4 element 50; Col. 6 lines 20-31, weighted coefficient would be applied to all pixels starting from the first pixel).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to apply scaling in the device disclosed by Kim. The motivation would have been to perform the smoothing operation (Hauck; Col. 6 lines 19-23).
As to claim 19, Kim (Fig. 6) discloses the electronic device of claim 18, comprising the electronic display, wherein the electronic display comprises the second processing circuitry (220).
As to claim 20, Kim (Fig. 6) discloses the electronic device of claim 19, wherein the second processing circuitry (220) is a component of a display driver integrated circuit (250, 230) of the electronic display (Para. 0072).
As to claim 21, Kim (Fig. 7) discloses the electronic device of claim 18, comprising a processor core complex (310), wherein the first processing circuitry (I/O device) and the second processing circuitry (360) are components of the processor core complex (Para. 0076).
As to claim 22, Kim discloses the electronic device of claim 18, wherein the second processing circuitry is configured to adjust the image data to compensate for the coupling between the display pixels and the data lines of the electronic display based on differences between the image data associated with adjacent display pixels that share the same data line (Para. 0068).
As to claim 23, Kim (Fig. 4) discloses the electronic device of claim 18, wherein the first line, the second line, the third line, and the fourth line (Row1 – Row4) are perpendicular to the data lines (DL).
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Hauck as applied to claims 3, 7, 12 and 14 above, and further in view of Hauck et al. (US Patent No. 6,091,426; hereinafter “Hauck”).
As to claim 8, Kim does not disclose the image processing circuitry of claim 7, comprising an image data difference line buffer configured to hold N+1 lines of differences.
However, Hauck (Fig. 7) teaches comprising an image data difference line buffer (103a, 103b) configured to hold N+1 lines of differences (Col. 7 lines 30-35).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to include a line buffer in the device disclosed by Kim. The motivation would have been to store the data signals (Hauck; Col. 8 lines 23-25).
As to claim 9, Kim does not disclose the image processing circuitry of claim 8, comprising scaling circuitry configured to apply a scaling factor to the differences from the image data difference line buffer based on a programming sequence of the image data that produced the differences.
However, Hauck teaches comprising scaling circuitry configured to apply a scaling factor to the differences from the image data difference line buffer based on a programming sequence of the image data that produced the differences (Fig. 4 element 50; Col. 6 lines 20-31, weighted coefficient would be applied to all pixels starting from the first pixel).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to applying scaling in the device disclosed by Kim. The motivation would have been to perform the smoothing operation (Hauck; Col. 6 lines 19-23).
Allowable Subject Matter
Claims 1-5, 12 and 14-17 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art, alone or in an obvious combination, does not disclose the limitations of independent claim 1 - “wherein the first scaled difference corresponds to a difference between first pixel data and second pixel data scaled based on a separation between the first column and the second column, and wherein the second scaled difference corresponds to a difference between third pixel data and fourth pixel data scaled based on a separation between the third column and the fourth column”.
The similar idea is embodied in the independent claim 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Winzell et al. (US 2024/0153050 A1) discloses applying scaler to the pixel difference values (Para. 0075).
Castleberry (US Patent No. 4,873,516)) discloses eliminating cross-talk in display (Abstract).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPIN GYAWALI whose telephone number is (571)272-1597. The examiner can normally be reached M-F 8:00-4:30 PM.
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BIPIN GYAWALI
Primary Examiner
Art Unit 2625
/BIPIN GYAWALI/Primary Examiner, Art Unit 2625
