Prosecution Insights
Last updated: April 19, 2026
Application No. 19/049,940

Electronic Display Self-Coupling Cross Talk Compensation

Non-Final OA §102§103
Filed
Feb 10, 2025
Examiner
GYAWALI, BIPIN
Art Unit
2625
Tech Center
2600 — Communications
Assignee
Apple Inc.
OA Round
1 (Non-Final)
58%
Grant Probability
Moderate
1-2
OA Rounds
2y 11m
To Grant
58%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allow Rate
217 granted / 374 resolved
-4.0% vs TC avg
Minimal -0% lift
Without
With
+-0.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
28 currently pending
Career history
402
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
64.4%
+24.4% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 374 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-22 are currently pending in the instant application. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 5-7, 9-12, 14 and 16-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2016/0240128 A1, hereinafter “Kim”). As to claim 1, Kim (Fig. 6) discloses an electronic display (200) comprising: an electronic display panel (210) comprising lines (SLn) and columns of display pixels (DLm), wherein each column of display pixels (Fig. 4 element Px) is coupled to a respective data line (1st DL); and display driver circuitry (Fig. 6 element 240) configured to adjust image data associated with the display pixels to account for coupling between the display pixels (Fig. 4 element Px) and the respective data lines (1ST DL – (M+1)TH DL; Para. 0063, 0067-0068). As to claim 2, Kim discloses the electronic display of claim 1, wherein the display driver circuitry is configured to adjust the image data based on image data differences associated with adjacently programmed display pixels coupled to the same respective data line (Fig. 5; Para. 0068). As to claim 3, Kim discloses the electronic display of claim 2, wherein the display driver circuitry is configured to adjust the image data based on a sum of a subset of the image data differences (Para. 0068, “The coupling voltage calculator can output the mean value of the amounts of the coupling C of the Mth data line 510 as the line coupling voltage Vc of the Mth data line 510”). As to claim 5, Kim discloses the electronic display of claim 1, wherein the display driver circuitry comprises a lookup table that outputs an adjustment value associated with a target display pixel based on a weighted sum of image data differences occurring on subsequent display pixels to be programmed after the target display pixel is to be programmed (Para. 0062, 0064, average, mean value). As to claim 6, Kim (Fig. 1) discloses an Image processing circuitry (100) comprising: an image data line buffer (110) configured to store lines of image data corresponding to lines of display pixels of an electronic display (Para. 0060); difference circuitry (130) configured to obtain an image data difference between pixel data of the image data associated with display pixels configured to be consecutively programmed via a shared data line (Para. 0062); and a pixel compensation lookup table (150) configured to generate a pixel data adjustment corresponding to pixel data of the image data associated with a target display pixel based on the image data difference (Para. 0064). As to claim 7, Kim discloses the image processing circuitry of claim 6, wherein the image data line buffer is configured to store N+1 lines of image data and the target display pixel is in a first line of the N+1 lines of image data in order of programming on the electronic display (Para. 0061, pixel value of first pixel). As to claim 9, (Original) The image processing circuitry of claim 8, comprising scaling circuitry configured to apply a scaling factor to the differences from the image data difference line buffer based on a programming sequence of the image data that produced the differences. As to claim 10, (Original) The image processing circuitry of claim 7, wherein the number N is greater than 2. As to claim 11, Kim (Fig. 6) discloses the image processing circuitry of claim 6, comprising addition circuitry (250) configured to add the pixel data adjustment to the pixel data of the image data associated with the target display pixel before the pixel data of the image data associated with the target display pixel is programmed into the target display pixel (Para. 0064). As to claim 12, Kim (Fig. 1) discloses a method (100) comprising: receiving, into a buffer (110), first pixel data corresponding to a first display pixel of a first line coupled to a first data line of an electronic display (Para. 0060, grayscale for (N-1)th row); receiving, into the buffer, second pixel data corresponding to a second display pixel of a second line coupled to the first data line of the electronic display (Para. 0060, grayscale for Nth row); determining a first pixel data compensation (Vdc) based at least in part on a difference between the first pixel data and the second pixel data (Para. 0063); and applying the first pixel data compensation to the first pixel data before the first pixel data is programmed into the first display pixel of the electronic display (Gc; Para. 0064). As to claim 14, Kim discloses the method of claim 12, comprising receiving, into the buffer, third pixel data corresponding to a third display pixel of a third line coupled to the first data line of the electronic display (Para. 0060); wherein the first pixel data compensation is determined based at least in part on a difference between the second pixel data and the third pixel data (Para. 0062, mean or average value of couplings of the data line). As to claim 16, The method of claim 12, wherein determining the first pixel data compensation comprises: determining a sum of scaled differences comprising a sum of at least: a first scaled difference corresponding to the difference between the first pixel data and the second pixel data scaled based on a separation between the first line and the second line; and at least another scaled difference between first other pixel data and second other pixel data, wherein the first other pixel data and the second other pixel data correspond to respective display pixels located on different lines and coupled to the first data line, scaled based on a separation between the different lines; and selecting the first pixel data compensation from a lookup table indexed to the first pixel data and the sum of scaled differences. As to claim 17, Kim (Fig. 6) discloses the method of claim 12, wherein the method is performed in display driver circuitry (230) of the electronic display (200; Para. 0064). As to claim 18, Kim (Fig. 6) discloses an electronic device (200) comprising: first processing circuitry configured to generate image data (Para. 0060, external device); and second processing circuitry (220) configured to adjust the image data to compensate for coupling between display pixels and data lines of an electronic display (210; Para. 0070). As to claim 19, Kim (Fig. 6) discloses the electronic device of claim 18, comprising the electronic display, wherein the electronic display comprises the second processing circuitry (220). As to claim 20, Kim (Fig. 6) discloses the electronic device of claim 19, wherein the second processing circuitry (220) is a component of a display driver integrated circuit (250, 230) of the electronic display (Para. 0072). As to claim 21, Kim (Fig. 7) discloses the electronic device of claim 18, comprising a processor core complex (310), wherein the first processing circuitry (I/O device) and the second processing circuitry (360) are components of the processor core complex (Para. 0076). As to claim 22, Kim discloses the electronic device of claim 18, wherein the second processing circuitry is configured to adjust the image data to compensate for the coupling between the display pixels and the data lines of the electronic display based on differences between the image data associated with adjacent display pixels that share the same data line (Para. 0068). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4, 8, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 3, 7, 12 and 14 above, and further in view of Hauck et al. (US Patent No. 6,091,426; hereinafter “Hauck”). As to claim 4, Kim does not disclose the electronic display of claim 3, wherein the display driver circuitry is configured to adjust the image data based on the sum of the subset of the image data differences scaled according to a programming time occurring after a target display pixel is to be programmed. However, Hauck (Fig. 4) teaches wherein the display driver circuitry is configured to adjust the image data based on the sum of the subset of the image data differences scaled according to a programming time occurring after a target display pixel is to be programmed (50; Col. 6 lines 20-31, inputting of data is considered to be the start of the programming time). It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to applying scaling in the device disclosed by Kim. The motivation would have been to perform the smoothing operation (Hauck; Col. 6 lines 19-23). As to claim 8, Kim does not disclose the image processing circuitry of claim 7, comprising an image data difference line buffer configured to hold N+1 lines of differences. However, Hauck (Fig. 7) teaches comprising an image data difference line buffer (103a, 103b) configured to hold N+1 lines of differences (Col. 7 lines 30-35). It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to include a line buffer in the device disclosed by Kim. The motivation would have been to store the data signals (Hauck; Col. 8 lines 23-25). As to claim 13, Kim does not disclose the method of claim 12, wherein determining the first pixel data compensation comprises scaling the difference between the first pixel data and the second pixel data based on a separation between the first line and the second line. However, Hauck teaches wherein determining the first pixel data compensation comprises scaling the difference between the first pixel data and the second pixel data based on a separation between the first line and the second line (Fig. 4 element 50; Col. 6 lines 20-31, weighted coefficient would be applied to all pixels). It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to applying scaling in the device disclosed by Kim. The motivation would have been to perform the smoothing operation (Hauck; Col. 6 lines 19-23). As to claim 15, Kim does not disclose the method of claim 14, wherein determining the first pixel data compensation comprises scaling the difference between the second pixel data and the third pixel data based on a separation between the second line and the third line. However, Hauck teaches wherein determining the first pixel data compensation comprises scaling the difference between the second pixel data and the third pixel data based on a separation between the second line and the third line (Fig. 4 element 50; Col. 6 lines 20-31, weighted coefficient would be applied to all pixels). It would have been obvious to one of ordinary skill in the art to combine the teaching of Hauck to applying scaling in the device disclosed by Kim. The motivation would have been to perform the smoothing operation (Hauck; Col. 6 lines 19-23). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure. Winzell et al. (US 2024/0153050 A1) discloses applying scaler to the pixel difference values (Para. 0075). Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPIN GYAWALI whose telephone number is (571)272-1597. The examiner can normally be reached M-F 9:00-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Will Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BIPIN GYAWALI Examiner Art Unit 2625 /BIPIN GYAWALI/Examiner, Art Unit 2625
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Prosecution Timeline

Feb 10, 2025
Application Filed
Dec 02, 2025
Response after Non-Final Action
Jan 07, 2026
Non-Final Rejection — §102, §103
Apr 01, 2026
Interview Requested
Apr 07, 2026
Applicant Interview (Telephonic)
Apr 08, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
58%
Grant Probability
58%
With Interview (-0.2%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 374 resolved cases by this examiner. Grant probability derived from career allow rate.

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