Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Continuation filed on 2/10/2025.
Claims 1-20 are pending for this examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/05/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Obvious-Type Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4-6, 9-12, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-6, 9-12, 18-19, and 22 of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286). Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1, 4-6, 9-12, and 18-20 of instant Application, respectively contains every element of claims 1, 4-6, 9-12, 18-19, and 22 of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286), as listed below, where Examiner has underlined the differences, and put in bold limitations that are rearranged but still mean the same thing between the two claim sets:
Claims
Instant Claims
Claims
U.S. Patent No. 11,308,017 (parent application s/n 16/858,286)
Independent claim 1
A method, comprising:
receiving, at a first command/address (CA) interface, a command indicating a configuration of a plurality of CA interfaces including the first CA interface, wherein each CA interface of the plurality of CA interfaces is coupled with a respective memory array of a plurality of memory arrays;
deactivating a second CA interface of the plurality of CA interfaces from a second memory array of the plurality of memory arrays such that the second CA interface is isolated based at least in part on receiving the command; and
coupling the first CA interface with the second memory array based at least in part on deactivating the second CA interface.
Independent claim 1
A method, comprising:
receiving, at a first command/address (CA) interface coupled with a first memory array, a command indicating a configuration of a plurality of CA interfaces including the first CA interface, wherein each CA interface of the plurality of CA interfaces is coupled with a respective memory array of a plurality of memory arrays comprising at least the first memory array;
isolating a second CA interface of the plurality from a second memory array of the plurality of memory arrays based at least in part on receiving the command; and
coupling the first CA interface with the second memory array based at least in part on isolating the second CA interface from the second memory array, wherein the first CA interface is coupled with both the first memory array and the second memory array based at least in part on the configuration.
Analysis
Examiner points out that the instant claimed are a broader version of the already allowed claimed of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286), where the instant claims have the same limitations but with fewer words and where the instant claims also indicate a deactivating the second CA interface instead of just isolating the second CA interface, but the meaning is the same as the purpose of the deactivation is isolating the second CA interface as specifically written in the claim language of the instant claims within the same limitation paragraph. As such the instant claims would be anticipated by the already allowed claims of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286).
Independent claim 11
An apparatus, comprising:
a first command/address (CA) interface coupled with a first control channel and associated with a first memory array;
a second CA interface coupled with a second control channel and associated with a second memory array; and
a selection component coupled with the first CA interface and the second CA interface and configured to selectively couple the second memory array with the first CA interface at a first time and to selectively couple the second memory array with the second CA interface at a second time, wherein the first CA interface is coupled with the first memory array at the first time and the second time.
Independent claim 11
An apparatus, comprising:
a first memory array coupled with a first data channel, the first data channel configured to communicate first data between the first memory array and a memory controller;
a second memory array different than the first memory array and coupled with a second data channel, the second data channel configured to communicate second data between the second memory array and the memory controller;
a first command/address (CA) interface coupled with a first control channel and associated with the first memory array;
a second CA interface coupled with a second control channel and associated with the second memory array; and
a selection component coupled with the first CA interface and the second CA interface and configured to selectively couple the second memory array with the first CA interface at a first time and to selectively couple the second memory array with the second CA interface at a second time, wherein the first CA interface is coupled with the first memory array at the first time and the second time.
Analysis
Examiner points out that the instant claims here are clearly a broader version of the already allowed claims of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286), where the instant claims are a word for word copy of what limitations are common between the two claim sets but noticeably the instant claims have fewer limitations overall. As such the instant claims would be anticipated by the already allowed claims of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286).
Independent claim 20
A method, comprising:
receiving a read command at a command/address (CA) interface, a first memory array and a second memory array, the first memory array coupled with a first data channel and the second memory array coupled with a second data channel different than the first data channel;
retrieving, based at least in part on identifying that the read command is for the second memory array, a set of data from the second memory array based at least in part on receiving the read command; and
transmitting the set of data over the second data channel based at least in part on retrieving the set of data from the second memory array.
Independent claim 22
A method, comprising:
receiving a read command at a command/address (CA) interface coupled with a first control channel, a first memory array, and a second memory array, the first memory array coupled with a first data channel and the second memory array coupled with a second data channel different than the first data channel;
identifying that the read command is for the second memory array;
retrieving a set of data from the second memory array based at least in part on receiving the read command; and
transmitting the set of data over the second data channel based at least in part on retrieving the set of data from the second memory array.
Analysis
Examiner points out that the instant claims here are clearly a broader version of the already allowed claims of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286), where the instant claims have all of the same limitations but rearranged where the claims of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286) also include an extra limitation of the CA interface coupled with a first control channel that is not in the instant claims. As such the instant claims would be anticipated by the already allowed claims of U.S. Patent No. 11,308,017 (parent application s/n 16/858,286).
Likewise, the corresponding dependent claims of the above cited independent claims carry similar limitations to each other respectively.
Claim Rejections - 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nguyen (US 7,406,572), herein referred to as Nguyen ‘572.
Referring to claim 11, Nguyen ‘572 teaches an apparatus (see Abstract; see Figs. 1-2, memory device 100), comprising:
a first command/address (CA) interface (see Fig. 2, MRAM interface 150) coupled with a first control channel (see Fig. 2, where MRAM interface 150 has a bus connecting to the MRAM cell arrays 180) and associated with the first memory array (see Fig. 2, MRAM cell array 180);
a second CA interface (see Fig. 1, NAND flash interface 120, NOR flash interface 130, CF flash interface 140) coupled with a second control channel (see Fig. 1, where the memory interfaces 120-150 have a bus connecting to the MRAM cell array 180, i.e. each interface having a bus connection to the MRAM cell array which may comprise multiple cell arrays, see Fig. 2) and associated with the second memory array (see Fig. 2, MRAM cell array 180 that comprises multiple cell arrays); and
a selection component (see Fig. 1, configuration block 170; see Col. 11, lines 19-47, where configuration block 170 may be used to selectively activate at least one memory interface block 120-150 for accessing MRAM array 180) coupled with the first CA interface and the second CA interface (see Fig. 1, memory interfaces 120-150) and configured to selectively couple the second memory array with the first CA interface at a first time and to selectively couple the second memory array with the second CA interface at a second time (see Col. 2, lines 21-41, wherein the configuration of the memory interface is done dynamically to select desired hardware and pin configurations; also see Col. 6, lines 11-53, wherein once an interface is selected, all other Flash memory interfaces may be disabled or placed in a power down mode, i.e. isolating an active interface and disabling other interfaces, and the configuration block determines appropriate mapping being the I/O pins of the I/O block 110 and the selected interface block to allow for communication through the selected interface, i.e. routing data from one MRAM cell array to a first memory interface at one time and routing data from a second MRAM cell array through a different memory interface at a second time), wherein the first CA is coupled with the first memory array at the first time and the second time (see Fig. 1, wherein all memory interfaces 120-150 are coupled with the MRAM cell array 180, and depending on how the configuration block 170 selects which interfaces to use may be activated / deactivated / reconfigured).
As to claim 12, Nguyen ‘572 teaches the apparatus of claim 11 (see Abstract; see Figs. 1-2, memory device 100), wherein: commands for the second memory array are received over the first control channel based at least in part on the second memory array being coupled with the first CA interface (see Col. 2, lines 21-41, wherein the configuration of the memory interface is done dynamically to select desired hardware and pin configurations, also see Col. 6, lines 11-53; see Fig. 3, wherein commands can be used to select pin configuration; also see Col. 6, lines 11-53, wherein once an interface is selected, all other Flash memory interfaces may be disabled or placed in a power down mode, i.e. isolating an active interface and disabling other interfaces, and the configuration block determines appropriate mapping being the I/O pins of the I/O block 110 and the selected interface block to allow for communication through the selected interface).
As to claim 13, Nguyen ‘572 teaches the apparatus of claim 11 (see Abstract; see Figs. 1-2, memory device 100), further comprising: a third CA interface associated with a third memory array; and a fourth CA interfaces associated with a fourth memory array, wherein the selection component is coupled with the third CA interface and the fourth CA interface (see Figs. 1-2, where there are 4 different memory interfaces, NAND flash interface 120, NOR flash interface 130, CF flash interface 140, smart MRAM interface 150, that are used to connect to MRAM cell arrays 180, which can comprise of multiple MRAM cell arrays, see Fig. 2).
As to claim 14, Nguyen ‘572 teaches the apparatus of claim 13 (see Abstract; see Figs. 1-2, memory device 100), wherein the first CA interface is coupled with the first memory array, the second memory array, the third memory array, and the fourth memory array using the selection component (see Figs. 1-2, where the memory interfaces 120-150 are coupled with MRAM cell arrays 180 and configuration block 170; see Col. 11, lines 19-47, where configuration block 170 may be used to selectively activate at least one memory interface block 120-150 for accessing MRAM array 180).
As to claim 15, Nguyen ‘572 teaches the apparatus of claim 13 (see Abstract; see Figs. 1-2, memory device 100), wherein the selection component is further configured to couple the fourth memory array with the third CA interface or the fourth CA interface (see Col. 2, lines 21-41, wherein the configuration of the memory interface is done dynamically to select desired hardware and pin configurations; also see Col. 6, lines 11-53, wherein once an interface is selected, all other Flash memory interfaces may be disabled or placed in a power down mode, i.e. isolating an active interface and disabling other interfaces, and the configuration block determines appropriate mapping being the I/O pins of the I/O block 110 and the selected interface block to allow for communication through the selected interface; see Col. 11, lines 19-47, where configuration block 170 may be used to selectively activate at least one memory interface block 120-150 for accessing MRAM array 180).
As to claim 16, Nguyen ‘572 teaches the apparatus of claim 13 (see Abstract; see Figs. 1-2, memory device 100), wherein the selection component is further configured to couple the third memory array with the first CA interface or the third CA interface and to couple the fourth memory array with the first CA interface or the fourth CA interface (see Col. 2, lines 21-41, wherein the configuration of the memory interface is done dynamically to select desired hardware and pin configurations; also see Col. 6, lines 11-53, wherein once an interface is selected, all other Flash memory interfaces may be disabled or placed in a power down mode, i.e. isolating an active interface and disabling other interfaces, and the configuration block determines appropriate mapping being the I/O pins of the I/O block 110 and the selected interface block to allow for communication through the selected interface; see Col. 11, lines 19-47, where configuration block 170 may be used to selectively activate at least one memory interface block 120-150 for accessing MRAM array 180).
As to claim 17, Nguyen ‘572 teaches the apparatus of claim 13 (see Abstract; see Figs. 1-2, memory device 100), wherein the first memory array, the second memory array, the third memory array, and the fourth memory array or a combination thereof comprise volatile memory cells (see Col. 1, lines 25-40, where memory storage elements can be volatile or non-volatile type).
As to claim 18, Nguyen ‘572 teaches the apparatus of claim 11 (see Abstract; see Figs. 1-2, memory device 100), wherein the selection component comprises a multiplexer coupled with the first CA interface and the second CA interface (see Col. 11, lines 19-47, where configuration block 170 is used to selectively activate at least on memory interface block for accessing the MRAM array via programming means including programmable fuses, multiplexers, or software-implemented logic).
As to claim 19, Nguyen ‘572 teaches the apparatus of claim 18 (see Abstract; see Figs. 1-2, memory device 100), wherein the selection component further comprises a latching component configured to transmit a selection signal to the multiplexer (see Col. 11, lines 19-47; Examiner points out that latching components are a common component in memory devices).
Referring to claim 20, Nguyen ‘572 teaches a method (see Abstract), comprising:
receiving a read command (see Fig. 2, CMD signal being transmitted to I/O block 110 and subsequently MRAM interface 150; see Col. 8, lines 4-46, where MRAM control block 152 translates received signals such that these translated signals may be used to generate row and column information to access addressed portion of MRAM cell array 180, i.e. read/write commands) at a command/address (CA) interface (see Fig. 2, MRAM interface 150), a first memory array (see Fig. 2, MRAM cell array 180 which has multiple MRAMs) and a second memory array (see Fig. 2, MRAM cell array 180 which has multiple MRAMs), the first memory array coupled with a first control channel (see Fig. 2, bus connecting MRAM interface 150 and MRAM cell arrays 180), and the second memory array coupled with a second data channel different than the first data channel (see Col. 6, lines 54-67, Col. 7, lines 1-30, wherein MRAM cell array can be configured to be connected to and accessed by a plurality of different flash interfaces, i.e. a bus connecting each of the different flash interfaces connecting I/O block 110 to MRAM cell array 180);
retrieving, based at least in part on identifying that the read command is for the second memory array (see Col. 4, lines 20-28, wherein memory operations include read and write operations; see Col. 8, lines 65-67, Col. 9, lines 1-31, wherein memory operations are identified and forwarded to its respective interface and memory), a set of data from the second memory array based at least in part on receiving the read command (see Col. 10, lines 37-67, Col. 11, lines 1-14, wherein an exemplary read command would have appropriate commands sent to the selected memory array to retrieve data based on the command); and
transmitting the set of data over the second data channel based at least in part on retrieving the set of data from the second memory array (see Col. 10, lines 37-67, Col. 11, lines 1-14, wherein an exemplary read command would have appropriate commands sent to the selected memory array to retrieve data based on the command; see Col. 6, lines 11-53, wherein once an interface is selected, all other Flash memory interfaces may be disabled or placed in a power down mode, and the configuration block determines appropriate mapping being the I/O pins of the I/O block 110 and the selected interface block to allow for communication through the selected interface).
Allowable Subject Matter
Claims 1-10 are indicated as allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art teaches systems and methods for implementing interfaces to memory wherein a configuration can be done to the interface based on a received command to select a specific interface out of many interfaces to use for communication with the memory, however, the prior art does not fairly teach or suggest, individually or in combination, a memory system and method with a plurality of command / address (CA) interfaces or data channels couples to a plurality of memory arrays respectively, where a command is received at a first CA interface / data channel of a plurality of interfaces / data channels indicating the configuration of the plurality of CA interfaces coupled with respective memory arrays, where a second CA interface is deactivated from a second memory array such that the second CA interface / data channel is isolated based on the received command, and coupling a first CA interface with the second memory array based at least in part on the deactivating of the second interface as claimed. Examiner specifically finds prior arts teaching reconfiguring communication paths between devices such as memory, but finds that prior art does not specifically teach receiving a command at a C/A interface indicating the configuration of a plurality of CA interfaces, then deactivating a second CA interface from its respective second memory array and coupling a first CA with the second memory array in response to the deactivating as claimed. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Morrison et al. (US 10,884,951) teaches a system for disabling memory interfaces, memory interface including address circuitry and I/O circuitry to allow for reads and writes.
Perego et al. (US 2004/0186956) teaches a DRAM memory module system wherein the bus width is configurable.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL SUN/Primary Examiner, Art Unit 2183
Prosecution Insights