Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim 1, claim 12 and claim 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US 11908381 in view of Jeon (US 20100053182). Although the claims at issue are not identical, they are not patentably distinct from each other because they are obvious variation of each other. The dependent claims 2-11, 13-17 and 19-20 are also rejected by the dependency rule.
Current Application
US 11908381
1. A display driver, comprising: one or more inputs to receive image data and drive sequences from one or more external controllers;
a plurality of cache memories to store the image data;
a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data;
a parsing circuit to: receive the image data and the drive sequences;
update the plurality of cache memories based on the received image data; and
update one or more logical functions stored in the LUT memory based on the received drive sequences; LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics; and
one or more output circuits for providing the image data configured with the display characteristics to a display device via one or more output interfaces.
12. A method for driving a display, the method comprising:receiving, at a display driver, image data and drive sequences from one or more external controllers;storing the image data in a plurality of cache memories;
updating one or more logical functions stored in a look-up table (LUT) memory based on the received drive sequences,
the LUT memory having a bit width corresponding to a number of possible values for each pixel color component of the image data;
applying the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics; and
providing the image data configured with the display characteristics to a display device.
18. A display system, comprising:a display device;an image data processing circuit to generate image data and drive sequences;and a display driver comprising:one or more inputs to receive the image data and drive sequences from the image data processing circuit;a plurality of cache memories to store the image data;a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data;a parsing circuit to:receive the image data and the drive sequences;update the plurality of cache memories based on the received image data; andupdate one or more logical functions stored in the LUT memory based on the received drive sequences;LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics; andone or more output circuits for providing the image data configured with the display characteristics to the display device via one or more output interfaces.
1. A display driver, comprising: one or more inputs for receiving image data and drive sequences from one or more external controllers;
one or more cache memories for storing the image data; at least two separate sequence memories configured to separately store one or more portions of the drive sequence;
a parsing circuit configured to receive the image data and the drive sequences, and to update the one or more cache memories and at least two separate sequence memories in real-time, the separate sequence memories being executed in parallel and asynchronously for different sets of image data; and
one or more output circuits for providing the image data configured with the drive sequences to a display device via one or more output interfaces.
1. A display driver, comprising: one or more inputs for receiving image data and drive sequences from one or more external controllers;
one or more cache memories for storing the image data; at least two separate sequence memories configured to separately store one or more portions of the drive sequence;
a parsing circuit configured to receive the image data and the drive sequences, and to update the one or more cache memories and at least two separate sequence memories in real-time, the separate sequence memories being executed in parallel and asynchronously for different sets of image data; and
one or more output circuits for providing the image data configured with the drive sequences to a display device via one or more output interfaces.
1. A display driver, comprising: one or more inputs for receiving image data and drive sequences from one or more external controllers;
one or more cache memories for storing the image data; at least two separate sequence memories configured to separately store one or more portions of the drive sequence;
a parsing circuit configured to receive the image data and the drive sequences, and to update the one or more cache memories and at least two separate sequence memories in real-time, the separate sequence memories being executed in parallel and asynchronously for different sets of image data; and
one or more output circuits for providing the image data configured with the drive sequences to a display device via one or more output interfaces.
US 11908381 does not expressly disclose a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data; and update one or more logical functions stored in the LUT or cache memory based on the received drive sequences; LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics;
However, Jeon teaches a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data ([0007] [0045]); and
update one or more logical functions stored in the LUT or cache memory based on the received drive sequences (fig.2-3); LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics ([0048]);
Therefore, it would have been obvious to a person of ordinary skill in the art to combine US 11908381 with Jeon teaching so that it may include a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data; and update one or more logical functions stored in the LUT memory based on the received drive sequences; LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics;
The motivation is to provide a method of compensating image data that corresponds to the previous image data stored in the cache memory is outputted as compensating data that corresponds to the received image data.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 12-15, 18-20 s/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20100053182) in view of Kaehlar (US 20080043002).
Regarding claim 1 Jeon teaches a display driver (fig.1), comprising:
one or more inputs to receive image data ([0035] The timing controlling part 200 receives a synchronization signal 201 and image data 202);
a plurality of cache memories to store the image data (fig. 2, 234, 238);
a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data (fig.2, [0007] [0045]); a parsing circuit (fig.2, 230) to:
receive the image data and the drive sequences (fig.3, S101);
update the plurality of cache memories based on the received image data (fig.3, when S103 is Yes, S113, S115); and
update one or more logical functions stored in the LUT memory based on the received drive sequences (fig.3, when S103 is NO, S123) ;
LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics (fig.2); and
one or more output circuits for providing the image data configured with the display characteristics to a display device via one or more output interfaces (fig.1).
Jeon does not expressly teach drive sequences from one or more external controllers.
However, Kaehlar teaches drive sequences from one or more external controllers ([0057] the GPU 210 may drive the embedded image onto the active scan area of the LCD array 215).
Therefore, it would have been obvious to one of the skilled in the art to combine Jeon in light of Kaehlar so that it may include drive sequences from one or more external controllers.
The motivation is to provide a method of communicating with a plurality of registers in a display driver integrated circuit.
Regarding claim 2 Jeon teaches each pixel color component of the image data has an image data bit width; and the bit width of the LUT memory is 2 to the power of the image data bit width ([0045] The received image data of `m` bits and the compensating data having expanded bits corresponding to the inputted image data is stored in the LUT memory 231 as the one-dimensional LUT type. For example, ten-bit compensating data corresponds to eight-bit image data expanded by two bits.).
Regarding claim 3 Jeon teaches wherein: the image data bit width is 8 bits; and the bit width of the LUT memory is 256 bits ([0045] The received image data of `m` bits and the compensating data having expanded bits corresponding to the inputted image data is stored in the LUT memory 231 as the one-dimensional LUT type. For example, ten-bit compensating data corresponds to eight-bit image data expanded by two bits. It is obvious that the LUT memory is 256 bits as 8 bit image data so 2 to the 8 is 256 for LUT memory bits).
Regarding claim 4 Jeon teaches wherein at least the one or more inputs, the plurality of cache memories, the LUT memory, the parsing circuit, the LUT logic, and the one or more output circuits are provided on an integrated circuit (fig. 2).
Regarding claim 5 Jeon in view of Kaehler teaches wherein the integrated circuit comprises an application specific integrated circuit (ASIC) (Kaehler: [0027] display driver IC 220).
Regarding claim 6 Jeon in view of Kaehler teach wherein the ASIC comprises a display driver integrated circuit (DDIC) (Kaehler: [0027] display driver IC 220).
Regarding claim 7 Jeon in view of Kaehler teach wherein the one or more external controllers comprises an image data processing circuit (Kaehler: fig.2, GPU).
Regarding claim 8 Jeon in view of Kaehler teach wherein the image data processing circuit comprises a graphics processing unit (GPU) (Kaehler: fig.2, GPU).
Regarding claim 9 Jeon in view of Kaehler teach wherein an updated drive sequence is received from the image data processing circuit (Kaehler: fig.2, GPU) responsive to changes in the image data (Kaehler [0057] [0029] [0046]).
Regarding claim 10 Jeon teaches wherein the drive sequences each comprise at least one of the following: signal modulation characteristics, color durations for pixels, frame-rate, color sub-frame rate, bit-depth, color sequential duty-cycle, color-gamut, gamma, persistence, drive- voltages, illumination timing, illumination intensity, timing of individual bit-planes sent to the display, LookUp Tables (LUTs) (fig.2: LUT), or serial port interface (SPI) commands.
Regarding claim 12 the limitations are similar to the limitations of claim 1 so rejected same way.
Regarding claim 13 the limitations are similar to the limitations of claim 2 so rejected same way.
Regarding claim 14 the limitations are similar to the limitations of claim 3 so rejected same way.
Regarding claim 15 Jeon teaches wherein a timer increment associated with the application of the one or more logical functions to the pixel color components comprises a video synchronization (VSync) signal ([0035] The timing controlling part 200 receives a synchronization signal 201 and image data 202. The image data 202 is digital data corresponding to gray-scales of an image. The timing controlling part 200 generates a plurality of timing signals for driving the display device using the synchronization signal 201. For example, the timing controlling part 200 generates data controlling signals 210d for controlling operation of the data driving part 310 and gate controlling signals 210g for controlling operation of the gate driving part 330. The data controlling signals 210d may include a horizontal synchronization signal, a load signal, an inversion signal, a data clock signal, etc. The gate controlling signals 210g may include a vertical synchronization signal,).
Regarding claim 18 Jeon teach a display system, comprising: a display device (fig.1);
an image data ([0035] The timing controlling part 200 receives a synchronization signal 201 and image data 202);
and a display driver (fig.1) comprising:
one or more inputs to receive the image data (fig. 2, 234, 238) and drive sequences from the image data processing circuit (fig.3,);
a plurality of cache memories to store the image data (fig. 3);
a look-up table (LUT) memory having a bit width corresponding to a number of possible values for each pixel color component of the image data ([0007] [0045]);
a parsing circuit to:
receive the image data and the drive sequences (fig.3, S101);
update the plurality of cache memories based on the received image data; and
update one or more logical functions stored in the LUT memory based on the received drive sequences (fig.3, when S103 is NO, S123);
LUT logic to apply the one or more logical functions stored in the LUT memory to pixel color components of the image data to configure the image data stored in the plurality of cache memories with display characteristics (fig.2); and
one or more output circuits for providing the image data configured with the display characteristics to the display device via one or more output interfaces (fig.1).
Jeon does not expressly teach processing circuit to generate image data and drive sequences ([0057] the GPU 210 may drive the embedded image onto the active scan area of the LCD array 215);
However, Kaehler teach processing circuit (fig.1) to generate image data and drive sequences ([0057] the GPU 210 may drive the embedded image onto the active scan area of the LCD array 215);
Therefore, it would have been obvious to one of the skilled in the art to combine Jeon in light of Kaehlar so that it may include processing circuit to generate image data and drive sequences.
The motivation is to provide a method of communicating with a plurality of registers in a display driver integrated circuit.
Regarding claim 19 the limitations are similar to the limitations of claim 2 so rejected same way.
Regarding claim 20 the limitations are similar to the limitations of claim 3 so rejected same way.
Claim(s) 11, 17 s/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20100053182) in view of Kaehlar (US 20080043002) and further in view of Iverson (US 20210210046).
Regarding claim 11 Jeon is silent on wherein the image data is formatted in at least one of a mobile industry processor interface (MIPI) format, a high-definition multimedia interface (HDMI) format, a display port (DP) format, a PCI-express format, a USB format, an Ethernet format, or a Wi-Fi format.
However, Iverson teaches wherein the image data is formatted in at least one of a mobile industry processor interface (MIPI) format, a high-definition multimedia interface (HDMI) format, a display port (DP) format, a PCI-express format, a USB format, an Ethernet format, or a Wi-Fi format ([0051] the drive scheme module 122 formats the image data frames 140 into MIPI image frame. The MIPI image frames are modified to replace some of the pixels of an image frame with drive scheme (control structure) information. While MIPI image frames are one specific example implementation, other image or video formats may also be used by the drive scheme module 122. Examples of other image or video formats that may be used or modified for the concurrent transmission of drive scheme and image data, include, but are not limited to, HDMI (high-definition multimedia interface), DP (display port), PCI-express, USB, Ethernet, and Wi-Fi).
Therefore, it would have been obvious to one of the skilled in the art to combine Jeon in light of Iverson so that it may include wherein the image data is formatted in at least one of a mobile industry processor interface (MIPI) format, a high-definition multimedia interface (HDMI) format, a display port (DP) format, a PCI-express format, a USB format, an Ethernet format, or a Wi-Fi format.
The motivation is to provide an image system that dynamically updates drive sequences in an image system.
Regarding claim 17 Jeon in view of Iverson teach wherein the image data comprises video data (Iverson: [0022]).
Allowable Subject Matter
Claim 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
-Walton US 20070188814
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/TOWFIQ ELAHI/Primary Examiner, Art Unit 2625