NON-FINAL REJECTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
TITLE OF THE INVENTION: See 37 CFR 1.72(a) and MPEP § 606. The title of the invention should be placed at the top of the first page of the specification unless the title is provided in an application data sheet. The title of the invention should be brief but technically accurate and descriptive, preferably from two to seven words. It may not contain more than 500 characters.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
ABSTRACT: Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The abstract of the instant specification appears to recite the independent claims and is not descriptive. The abstract should be rewritten to be a clear and concise narrative of the invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (US 2020/0326884).
Regarding claim 1, Hu discloses:
A storage device, comprising:
a memory device comprising a plurality of planes (FIG. 1A/FIG. 3 Non-volatile memory; [0012] the die of the non-volatile memory 150 as shown in FIG. 1A has a 2-plane die configuration), wherein each of the plurality of planes is provided in one of a plurality of banks of the memory device ([0037] For processing more data, the eight dies 30˜37 operated according to the chip enable signal CE0 are collaboratively formed as a bank (e.g., bank0). The eight dies 40˜47 operated according to the chip enable signal CE1 are collaboratively formed as another bank (e.g., bank1). The rest may be deduced by analogy; i.e., each die has a plane-based configuration and each bank has a plurality of banks); and
a memory controller (FIG. 4A Control circuit 410) configured to:
receive, from a host, a plurality of jobs to be performed on the memory device, the plurality of jobs comprising a plane-level job to be performed in a plane from among the plurality of planes ([0010] in the multi-plane configuration, a single block or plural blocks corresponding to the plane in each die are selected, and the selected blocks of the plural dies are collaboratively defined as the superblock; [0046] the solid state drive 400 is connected with a host (not shown). The write command from the host contains a stream information. According to the stream information, the control circuit 410 confirms the data streams and stores the write data of different data streams into the corresponding open superblocks of the non-volatile memory 450; [0048] the control circuit 410 further comprises a stream job link list 416 for managing the jobs corresponding to all data streams; FIG. 5A);
determine, for each of the plurality of planes at a first time, a target bank from among the plurality of banks based on plane information associated with a job from among the plurality of jobs that is pending in the storage device ([0041] In the bank-based non-volatile memory, a job is defined according to the unit program data amount of the bank (the working unit), and the program operation is performed on the bank of the corresponding open superblock (i.e., plane information) according to the job. For example, each bank contains 8 pages, and the data amount of each page of the die is 16K bytes. That is, the program data amount is 128K bytes (i.e., 8×16K bytes=128K bytes), and the write data is divided into plural groups of program data according to the program data amount. In the multi-plane configuration, where M blocks corresponding to the plane in each die are selected and collaboratively defined as the superblock, the program data amount is M×128K bytes, and the write data is divided into plural groups of program data according to the program data amount. Then, one program command is assigned to each group, and the group and the program command are defined as a job. Then, the job is assigned to the bank of the open superblock); and
transmit the job for the target bank to the memory device (FIG. 4B The jobs corresponding to the data streams are transmitted from the control circuit to the corresponding superblock of the non-volatile memory through the corresponding channels according to the content of the stream job link list).
Regarding claim 17, Hu further discloses:
The storage device of claim 1, wherein the memory device is configured to:
perform the plurality of jobs in the plurality of banks ([0059] since the non-volatile memory 450 contains four banks (e.g., bank0˜bank3), four jobs are cyclically executed by the control circuit 410. That is, the four jobs of each data stream can be programmed to one superpage of one superblock. For example, the four jobs (e.g., job0˜job3) in a cycle and in the write data of each data stream are correlated with the four banks (e.g., bank0˜bank3) and programmed to a superpage of an open superblock. Moreover, the four jobs (e.g., job0˜job3) in the next cycle are correlated with the four banks (e.g., bank0˜bank3) and programmed to the next superpage of the same open superblock); and
transmit, to the memory controller, data generated by performing the plurality of jobs to the host ([0006] according to a read command from the host 110, the control circuit 120 acquires a read data from the non-volatile memory 150. Then, the read data is transmitted from the control circuit 120 to the host 110).
Regarding claim 18, Hu further discloses:
The storage device of claim 1, wherein the plane-level job is a read job, a write job, or an erase job ([0043] FIG. 4A is a schematic function block diagram illustrating the architecture of a multi-stream write solid state drive according to an embodiment of the present invention).
Regarding claim 20, Hu discloses:
A method for operating a storage device, the method being performed by a memory controller (FIG. 4A Control circuit 410) and comprising:
receiving a plurality of jobs to be performed on a memory device (FIG. 1A/FIG. 3 Non-volatile memory; [0012] the die of the non-volatile memory 150 as shown in FIG. 1A has a 2-plane die configuration; [0037] For processing more data, the eight dies 30˜37 operated according to the chip enable signal CE0 are collaboratively formed as a bank (e.g., bank0). The eight dies 40˜47 operated according to the chip enable signal CE1 are collaboratively formed as another bank (e.g., bank1). The rest may be deduced by analogy; i.e., each die has a plane-based configuration and each bank has a plurality of banks), the plurality of jobs comprising a plane-level job to be performed in a plane from among a plurality of planes of the memory device, wherein each of the plurality of planes is included in one of a plurality of banks of the memory device ([0010] in the multi-plane configuration, a single block or plural blocks corresponding to the plane in each die are selected, and the selected blocks of the plural dies are collaboratively defined as the superblock; [0046] the solid state drive 400 is connected with a host (not shown). The write command from the host contains a stream information. According to the stream information, the control circuit 410 confirms the data streams and stores the write data of different data streams into the corresponding open superblocks of the non-volatile memory 450; [0048] the control circuit 410 further comprises a stream job link list 416 for managing the jobs corresponding to all data streams; FIG. 5A);
determining, for each of the plurality of planes at a specific time, one of the plurality of banks to be a target bank based on plane information associated with a job pending in at least one of the memory device or the memory controller ([0041] In the bank-based non-volatile memory, a job is defined according to the unit program data amount of the bank (the working unit), and the program operation is performed on the bank of the corresponding open superblock (i.e., plane information) according to the job. For example, each bank contains 8 pages, and the data amount of each page of the die is 16K bytes. That is, the program data amount is 128K bytes (i.e., 8×16K bytes=128K bytes), and the write data is divided into plural groups of program data according to the program data amount. In the multi-plane configuration, where M blocks corresponding to the plane in each die are selected and collaboratively defined as the superblock, the program data amount is M×128K bytes, and the write data is divided into plural groups of program data according to the program data amount. Then, one program command is assigned to each group, and the group and the program command are defined as a job. Then, the job is assigned to the bank of the open superblock); and
transmitting, among the plurality of jobs that are waiting in the memory controller, a waiting job for the target bank to the memory device (FIG. 4B The jobs corresponding to the data streams are transmitted from the control circuit to the corresponding superblock of the non-volatile memory through the corresponding channels according to the content of the stream job link list).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hu and Nishino et al. (US 2023/0089083).
Regarding claim 19, Hu discloses:
A memory controller, comprising:
…a memory device comprising a plurality of planes (FIG. 1A/FIG. 3 Non-volatile memory; [0012] the die of the non-volatile memory 150 as shown in FIG. 1A has a 2-plane die configuration), wherein each of the plurality of planes is provided in one of a plurality of banks of the memory device ([0037] For processing more data, the eight dies 30˜37 operated according to the chip enable signal CE0 are collaboratively formed as a bank (e.g., bank0). The eight dies 40˜47 operated according to the chip enable signal CE1 are collaboratively formed as another bank (e.g., bank1). The rest may be deduced by analogy; i.e., each die has a plane-based configuration and each bank has a plurality of banks);
…a host and configured to receive, from the host, a plurality of jobs to be performed on the memory device, the plurality of jobs comprising a plane- level job to be performed in a plane within the memory device ([0010] in the multi-plane configuration, a single block or plural blocks corresponding to the plane in each die are selected, and the selected blocks of the plural dies are collaboratively defined as the superblock; [0046] the solid state drive 400 is connected with a host (not shown). The write command from the host contains a stream information. According to the stream information, the control circuit 410 confirms the data streams and stores the write data of different data streams into the corresponding open superblocks of the non-volatile memory 450; [0048] the control circuit 410 further comprises a stream job link list 416 for managing the jobs corresponding to all data streams; FIG. 5A); and
…configured to:
determine, for each of the plurality of planes at a specific time, one of the plurality of banks to be a target bank based on plane information associated with a job pending in the memory device or the memory controller ([0041] In the bank-based non-volatile memory, a job is defined according to the unit program data amount of the bank (the working unit), and the program operation is performed on the bank of the corresponding open superblock (i.e., plane information) according to the job. For example, each bank contains 8 pages, and the data amount of each page of the die is 16K bytes. That is, the program data amount is 128K bytes (i.e., 8×16K bytes=128K bytes), and the write data is divided into plural groups of program data according to the program data amount. In the multi-plane configuration, where M blocks corresponding to the plane in each die are selected and collaboratively defined as the superblock, the program data amount is M×128K bytes, and the write data is divided into plural groups of program data according to the program data amount. Then, one program command is assigned to each group, and the group and the program command are defined as a job. Then, the job is assigned to the bank of the open superblock); and
transmit, among the plurality of jobs that are waiting in the memory controller, a waiting job for the target bank to the memory device through the memory interface circuit (FIG. 4B The jobs corresponding to the data streams are transmitted from the control circuit to the corresponding superblock of the non-volatile memory through the corresponding channels according to the content of the stream job link list).
Hu does not explicitly teach “a memory interface circuit connected to” a memory device, “a host interface circuit connected to” a host, and “a processor connected to the memory interface circuit and the host interface circuit, wherein the processor is configured to.” However, Nishino et al. disclose:
a memory interface circuit connected to a memory device (FIG. 1 Memory Interface 40)…
a host interface circuit connected to a host (FIG. 1 Host I/F 50)…
a processor connected to the memory interface circuit and the host interface circuit (), wherein the processor is configured to ([0034] A function of the control unit 30 is implemented by a system program (firmware) stored in the non-volatile memory 10 and a processor that executes the firmware. A part or all of the processes executed by the control unit 30 may be executed by dedicated hardware in the controller 60)…
Hu and Nishino et al. are analogous art because Hu and Nishino et al. teach accessing non-volatile memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hu and Nishino et al. before him/her, to modify the teachings of Hu with the Nishino et al. teachings of memory controller configuration because implementing a host interface, a memory interface, and a process within the memory controller would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 I.A.) A host interface is a well-known element for interfacing a memory controller with a host. A memory interface is a well-known element for interfacing a memory controller with a memory device. A processor is a well-known element of a memory controller for performing the operations of the memory controller. Implementing these elements within the Hu’s memory controller would have yielded the predictable result performing the functions taught by Hu.
Allowable Subject Matter
Claims 2-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the examiner’s statement of reasons for allowance:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Hu, when taken alone or in combination with the other prior art of record, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 2, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The storage device of claim 1, wherein the plane information comprises: for each of the plurality of banks, first plane information indicating a first number of planes for which there is a waiting job in the memory controller; and for each of the plurality of banks, second plane information indicating a second number of planes for which there is a running job in the memory device, and wherein the memory controller is further configured to determine the target bank based on the first number of planes and the second number of planes of each of the plurality of banks.”
Claims 3-15 would be allowable based on their dependency from claim 2.
Regarding claim 16, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The storage device of claim 1, wherein the memory controller is further configured to transmit, if a waiting job for the target bank is performed in the target bank, in response to determining that a number of planes performing the job in the target bank is greater than or equal to a threshold, the waiting job for the target bank to the memory device.”
Conclusion
The prior art made of record and not relied upon, Prakash et el. (US 2022/0083266) and Sankaranarayanan (US 2023/0068605) is considered pertinent to applicant's disclosure because they disclose accessing memory devices and the plane and bank level.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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