DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 02/11/2025, 06/23/2025 and 02/11/2026 have been considered by the examiner.
Claim Objections
Claims 13-20 are objected to because of the following informalities:
Claim 13, line 4 the recited “the sample circuit that includes a second set of analog-digital converter circuits” should be “the sample circuit further includes a second set of analog-to-digital converter circuits”.
Dependent claims 14-20 are also objected to since they depend on objected claim 13.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11, recites “…includes sampling, by the sample circuit, a first sample
buffer”. It is unclear what Applicant intends to claim by claiming sampling a first sample buffer. A sample buffer is a component. Sampling is performed on a signal not on a component.
Claim 12, recites “…includes sampling, by the sample circuit, a second sample
buffer”. Similar top claim 11, it is unclear what Applicant intends to claim by claiming sampling a second sample buffer. A sample buffer is a component. Sampling is performed on a signal not on a component.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pandita (U.S. 2022/0302951).
With respect to claim 13, Pandita discloses: An apparatus (receiver 20 of Fig. 3
and related Fig. 2, [0005]-[0006]), comprising: a sample circuit (the claimed sample circuit comprises the track and hold circuits 34 and the two sets of ADCs 60 [0023]) that includes a first set of analog-to-digital converter circuits (first set of ADCs 60B, comprising the ADCs of the odd channels [0023]) configured to generate odd samples (samples out of the ADCs of the odd channels); the sample circuit that includes a second set of analog-to-digital converter circuits (second set of ADCs 60A of the even channels) configured to generate even samples (the samples out of the ADCs of the even channels); and a recovery circuit (e.g. the equalizer 42 of Fig. 2, where FFE 44 and DFE 46 are also shown in Fig. 3, corresponds to the claimed recovery circuit, refer to at least the last two sentences of [0022] “The equalized digital data PAM represents one of the four PAM signal states 0, 1, 2, or 3”, and last 5 lines of [0001], one of the PAM signal states corresponds a recovered PAM data symbol. Also refer to Fig. 10 step 218. The continuous operation of the receiver outputs recovered data symbols and refer to the symbol transfer rate of [0024]) configured to generate recovered data symbols based on the odd samples and the even samples (refer to Fig. 3 (and related Fig. 2) and the portions of Pandita already cited above).
With respect to claim 20, Pandita discloses: wherein the sample circuit includes a re-timer circuit (refer to lines 1-4 of [0043], [0050] refer to at least retimers 140 which correct differential timing mode) configured to adjust a timing of the odd samples and of the even samples).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (U.S. 2007/0253475) in view of LaGasse et al. (U.S. 2002/0093993).
With respect to claim 1, Palmer et al. disclose:
An apparatus, comprising: a receiver circuit (receiver 710 of Fig. 7 [0033], [0035] or receiver 1300 of Fig. 13 [0055]), wherein the receiver circuit is configured to: sample (Fig. 7, refer to data sampler 730, lines 1-4 of [0035]. Alternatively refer to data sampler 1130 of Fig. 13), using a recovered clock signal (e.g. refer to clock CK0 (out of a not shown clock recovery circuit), second to last sentence of [0038] also [0021] describing a clock recovery circuitry), an equalized signal (730 samples equalized signal VEQ, lines 1-3 of [0034], lines 1-4 of [0035], or refer to Fig. 13, [0055], lines 1-4 of [0056)) at times corresponding to odd-numbered data symbols to generate odd samples (refer to the sections cited above related to the operation of sampler 730 or 1130), wherein the equalized signal is generated based on a plurality of signals that encode a serial data stream that includes a plurality of data symbols having the odd-numbered data symbols and even-numbered data symbols (the plurality of signals (e.g. the differential received DDR signals) that encode serial data (implicit in DDR transmission) into odd and even data symbols (lines 2-3 of [0024] and the odd and even data symbols sampled by the data samplers)); sample (Fig. 7 refer to sampler 732 or Fig. 13 refer to sampler1332), using a clock signal (CK180), the equalized signal at times corresponding to the even-numbered data symbols to generate even samples (lines 1-4 of [0035] or lines 1-4 of [0056]); and process the odd samples and the even samples to generate a plurality of recovered data symbols (Fig. 7 refer for example to the output of the deserializer 740 and register 742 [0035]-[0036] where the received data (data words) correspond to the claimed data symbols. Alternatively, refer to Fig. 13 the output of deserializer 1340 (data words) [0056]).
Palmer does not disclose: using the recovered clock signal.
Implementing clock generation, LaGasse et al disclose: using a recovered clock signal (lines 6-8 of [0079] “…processor 124 will shift the phase of the recovered clock signal via the phase shifter by 180 degrees “).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to sample (using sampler 732 or using sampler 1332), using the recovered clock signal (CK0 in Palmer) and by phase shifting the recovered clock using a phase shifter by 180 degrees (as taught by LaGasse et al.) to obtain CK180, so that using a known and suitable way of generating a clock signal that is 180 degree shifted than a recovered clock signal (obtain the predictable result of generating CK180 using CK0).
With respect to claim 2, modified Palmer wherein the odd samples and the even samples include mismatch, and wherein the receiver circuit is further configured to correct the mismatch (refer to the clocked deserializer 740 and [0036] “The purpose of signal DCLK is to retime all the data and edge samples into the same time domain…”, implying the data (odd and even) samples include mismatch (a time domain mismatch) corrected by using DCLK in 740).
With respect to claim 6, modified Palmer discloses: wherein the receiver circuit is further configured to adjust a timing of the odd samples and of the even samples (e.g. part of the claimed process of claim 1, using retimer (742) or retimer 1363).
Method claim 7 recites steps corresponding to the claimed functions of apparatus claim 1 and is rejected based on the rationale used to reject claim 1 above (the claimed sampler circuit of claim 7 comprises 730 and 732 or 1330 and 1332 of Fig.13 and the claimed recovery circuit comprises deserializer 740 and retimer 742 or 1340 and 1363).
With respect to claim 8, modified Palmer discloses: further comprising receiving, by the sample circuit, the equalized signal (refer to VEQ received by the sampler circuit (730 and 732 or 1330 and 1332)).
Claim 9 is rejected based on the rationale used to reject claim 1 above.
12. Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (U.S. 2007/0253475) in view of LaGasse et al. (U.S. 2002/0093993) and further in view of Sai (U.S. 2015/0160067).
With respect to claim 10, modified Palmer, LaGasse et al. do not disclose:
further comprising buffering, by the sample circuit, the equalized signal to drive analog-to-digital converter circuits of the sample circuit.
Implementing a sampler, Sai et al. disclose: further comprising buffering, by a sample circuit, a signal to drive (an) analog-to-digital converter circuit of the sample circuit (Fig. 1, refer to sampling unit 196 (sample circuit), 189 buffer amplifier buffers a sampled and held received signal lines 4-7 of [0019] to drive the ADC circuit of the sampling unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Palmer to including a sampling circuit as taught by Sai (including S&H 188, a buffer amplifier 189, and a ADC 191) to implement each of the samplers (of Fig. 7 or Fig. 13) to use components that are known and suitable for performing sampling, with a reasonable expectation of success (sampling of the equalized data signal of Palmer).
With respect to claim 11, as best understood, modified Palmer discloses: wherein sampling, by the sample circuit, the equalized signal at times corresponding to the odd-numbered data symbols includes sampling, by the sample circuit (e.g. refer to the sampling performed by 730 or 1330).
Modified Palmer, LaGasse et al. do not disclose: sampling, by the sample circuit, a first sample buffer.
Implementing a signal sampler, Sai et al. disclose: sampling, by a sample circuit, a first sample buffer (Fig. 1, refer to sampling unit 196 and at least lines 4-7 of [0019] sampling performed by the ADC on an output of the buffer amplifier 189)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Palmer to include a sampling circuit as taught by Sai (including S&H 188, a buffer amplifier 189, and a ADC 191) to implement (at least) sampler 730 or 1030 to use components that are known and suitable for performing sampling, with a reasonable expectation of success (sampling of the equalized data signal of Palmer).
With respect to claim 12, as best understood, modified Palmer discloses: wherein sampling, by the sample circuit, the equalized signal at times corresponding to the even-numbered data symbols includes sampling, by the sample circuit (e.g. refer to the sampling performed by 732 or 1332).
Modified Palmer, LaGasse et al. do not disclose: sampling, by the sample circuit, a second sample buffer.
Implementing a signal sampler, Sai et al. disclose: sampling, by a sample circuit, a second sample buffer (Fig. 1, refer to sampling unit 196 and at least lines 4-7 of [0019] sampling performed by the ADC on an output of the buffer amplifier 189)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Palmer to include a sampling circuit as taught by Sai (including S&H 188, a buffer amplifier 189, and a ADC 191) to implement (at least) sampler 732 or 1332 to use components that are known and suitable for performing sampling, with a reasonable expectation of success (sampling of the equalized data signal of Palmer).
13. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (U.S. 2007/0253475) in view of Jeon et al. (U.S. 11,658,648).
With respect to claim 13, Palmer et al. disclose: An apparatus (710 of Fig. 7), comprising: a sample circuit (e.g. Fig. 7 refer to sampler comprising samplers: 730, 735, 732, 737 , [0035]) that includes a first set of circuits configured to generate odd samples (Fig. 7 sampler includes a first set of samplers 730, 735, that generate odd samples (odd data samples and odd edge samples [0035]); the sample circuit that includes a second set of circuits (second set of samplers 732, 737) configured to generate even samples (that generate even samples (even data samples and even edge samples [0035]); and a recovery circuit configured to generate recovered data symbols (based on the odd samples and the even samples. (e.g. 740 and 742 [0035], and [0037] and approximate second half of [0038]. Refer to the outputting of the equalization control supplied (as an analog signal) to the EQ 725, and due to the loop arrangement of 710, the recovery circuit (740 and 742) generates the recovered data symbols (out of 742) based on previous odd and even samples used to adjust the equalizer 725).
Palmer et al. do not disclose: analog-to-digital converter circuits.
Implementing a sampler, Jeon et al. disclose: an analog-to-digital converter (a sampler includes an ADC (column 4, lines 49-53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include in each of the samplers of Palmer et al. an ADC, based on the cited teaching of Jeon et al. (a sampler including an ADC) to implement the first and second sets of samplers using a first set and a second set of ADCs, in order to use known and suitable components (ADCs) to perform the sampling of Palmer et al. (obtain the predictable result of sampling).
14. Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (U.S. 2007/0253475) in view of Jeon et al. (U.S. 11,658,648) and further in view of Jin et al. (U.S. 9,584,306).
With respect to claim 14, modified Palmer et al. disclose:
wherein: to generate the odd samples, the sample circuit is configured to sample, using a recovered clock signal (e.g. refer to clock CK0 (generated by a clock recovery circuitry, not shown) used by ADC (performing sampling using CK0) and at least the second to last sentence of [0038]), an equalized signal at times corresponding to odd-numbered data symbols (lines 1-4 of [0035] and using the ADC of modified Palmer. Note that “to generate the odd samples”, the sample circuit (ADCs performing sampling of 730 and 735) performs the operation claimed in lines 2-3 and an additional operation to generate the odd error sample(s)), the equalization signal generated based on a signal that encodes a data stream including the odd-numbered data symbols and even-numbered data symbols the plurality of signals (e.g. the differential received DDR signals) that encodes serial data (implicit in DDR transmission) including the odd and even data symbols (lines 2-3 of [0024] and the odd and even data symbols sampled by the data samplers)); and to generate the even samples, the sample circuit is configured to sample (ADC which implements sampling of 732), using a clock signal (CK180), the equalized signal at times corresponding to the even-numbered data symbols (lines 1-4 of [0035]. The sample circuit (ADCs performing sampling of 730 and 735 and ADCs performing sampling of 732 and 737) performs the operation claimed in lines 7-8 and an additional operation to generate the even error sample(s))).
Modified Palmer, Jeon et al. do not disclose: using the recovered clock signal
Implementing recovered clock generation, Jin et al. disclose: using a recovered clock , signal (column 6, lines 65-67, column 7, lines 1-4, using a recovered clock (0 degree phase) clocks having phase shifts of 90 degrees, 180 degrees and 270 degrees are obtained from the recovered clock).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Palmer et al. based on Jin et al. to use the recovered clock signal (CK0) to generate CK180 (by applying phase delays to CK0) as taught by Jin et al. to obtain CK180 using known components (phase delays) to obtain the predictable result of generating the 180-degree clock signal of Palmer.
With respect to claim 15, modified Palmer disclose: further comprising a front-end circuit (Fig. 7, refer to equalizer EQ 725, [0034]) configured to receive the signal that encodes the data stream, wherein the recovery circuit includes an offset circuit (refer to the clocked deserializer 740, [0036]), wherein the odd samples and the even samples include mismatch, and wherein the offset circuit is configured to correct the mismatch (“The purpose of signal DCLK is to retime all the (even and odd) data and (even and odd) edge samples into the same time domain…”, implying the odd and even samples include mismatch (a time domain mismatch) corrected by using DCLK in 740).
Allowable Subject Matter
15. Claims 3-5, 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bucher et al. (U.S. 9,148,187) refer to at least the system of Fig. 6 disclosing an even sample and hold circuit 125 and even sampling 620 circuit and an odd sample and hold circuit 130 and odd sampling 625 circuit. Refer to the calibration method of Fig. 8.
Zhou et al. (U.S. 8,879,616) refer the receivers of Fig. 3 and Fig. 6.
Contact Information
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA VLAHOS whose telephone number is (571)272-5507. The examiner can normally be reached M 8:00-4:00, TWRF 8:00-2:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SAM K AHN can be reached at 571-272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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SOPHIA VLAHOS
Examiner
Art Unit 2633
/SOPHIA VLAHOS/Primary Examiner, Art Unit 2633 07/17/2026
Prosecution Insights