DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 4 – 5, 7 - 11, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 - 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, in claim 16, there is no antecedent basis for, “said differential drive signal”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 3, 6 and 12 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 8.409,561 (Buter et al. hereinafter Buter) in view of U.S. Patent No. 9,515,617 (Hoyerby).
With respect to claim 1, Buter discloses:
“A switching driver circuit for driving a load”
Buter discloses a switching power stage configured to drive a load. Specifically, Buter states that a Class-D circuit comprises a switching power stage for driving a load, with the output being a PWM signal.
Buter, col. 1, ll. 18–21.
Buter further teaches use of a multilevel PWM signal and an output stage capable of reproducing multiple output levels.
Buter, col. 1, ll. 20–27.
“first and second output nodes for outputting a differential drive signal for driving the load”
Buter teaches two three-level switching stages connected so as to provide a differential signal across a load.
Specifically:
“FIG. 9 shows an implementation where two three-level switching stages 1 can be used in bridge configuration.”
Buter then expressly states that the arrangement:
“allows generating a 5-level differential voltage across the load.”
Buter, col. 4, ll. 12–17; Fig. 9.
“via a filter arrangement comprising an inductance in series with the load”
Buter does not cleanly disclose this limitation in the Fig. 9/10 embodiment.
Høyerby does.
Høyerby discloses first and second output nodes VA and VB coupled to a loudspeaker through respective output filtering arrangements. It specifically identifies first load inductor 414 and second load inductor 437 and corresponding load capacitors.
Hoyerby, Høyerby, col. 16, ll. 40–65; Fig. 4(b).
The disclosure continues by identifying the respective values of the second load inductor 437 and second load capacitor 423 coupled to the second output node.
Hoyerby, col. 16, ll. 40–65.
Accordingly, Høyerby supplies the claimed series inductance between the switching output and load.
“first and second supply nodes configured to receive respective first and second supply voltages”
Buter's switching circuitry operates between VS and ground.
Buter expressly describes its three available voltage levels as:
1 ground;
2 half supply voltage VS; and
3 supply voltage VS.
Buter, col. 1, ll. 37–39.
Thus VS constitutes the first supply voltage and ground constitutes the second supply voltage.
“an intermediate voltage node configured to receive an intermediate voltage provided by a driver capacitance”
Buter expressly teaches a capacitive divider that derives a voltage equal to half of the supply voltage.
Buter, col. 1, ll. 39–43; Fig. 2.
Buter further explains that capacitors C1 and C2 are alternately charged and discharged by load current and interchanged so that a voltage equal to one-half the supply voltage is continuously generated.
Buter, col. 1, ll. 37–59.
Thus Buter's capacitive divider supplies the claimed capacitor-derived intermediate voltage.
“wherein the intermediate voltage is between the first and second supply voltages”
Buter's disclosed switching voltages are:
VS — ½VS — ground.
Buter, col. 1, ll. 37–41.
Therefore, ½VS is expressly between the first supply voltage VS and the second supply voltage ground.
driver switch network permitting connection to the first supply, second supply, and intermediate voltage
Buter expressly teaches a switching stage in which output Vo can be switched:
• to ground by M7;
• to ½ supply voltage by M5; or
• to supply voltage by M6.
Buter, col. 3, ll. 45–52; Fig. 6. See also, that Buter expressly applies its three-level switching architecture in the differential arrangement of Fig. 9 and in the alternative configuration of Fig. 10. col. 4, ll. 12–45; Figs. 9–10.
“a controller configured to operate the driver switch network in a sequence of switch states based on an input signal”
Buter teaches that its switching power stage produces a PWM output and that a multilevel PWM signal more accurately represents the input signal.
Buter, col. 1, ll. 15–27.
For an express controller and switching-sequence implementation, Høyerby provides a more detailed teaching.
Høyerby discloses controller 1103 receiving the analog audio input signal, processing the resulting signal through loop filter 1117 and PWM circuit 1115, and producing a naturally sampled PWM signal.
Hoyerby, col. 24, ll. 28–65.
That PWM signal is provided to switching-pattern mapping circuit 1119, which generates the appropriately phased and timed PWM control signals for the semiconductor switches of power stage 1107.
Hoyerby, col. 25, ll. 1–9; Fig. 11.
Thus Hoyerby expressly establishes the relationship:
input signal → controller → PWM signal → switching pattern → semiconductor-switch states.
regulation of the intermediate voltage through operation of the switching network
Buter itself provides a particularly strong teaching here.
Regarding Fig. 10, Buter teaches that current in the capacitor may be positive or negative such that the capacitor voltage is maintained within a specified range.
Buter, col. 4, ll. 18–25.
Buter then expressly teaches:
a controller that decides between charge and discharge
for controlling the capacitor voltage.
Buter, col. 4, ll. 23–28.
The capacitor voltage is measured and a determination is made whether to charge or discharge the capacitor the next time it is connected to the load.
Buter, col. 4, ll. 27–32.
Buter additionally teaches that the controller can toggle between charging and discharging within the PWM pulse.
Buter, col. 4, ll. 29–32.
Accordingly, Buter expressly teaches regulation of the capacitor-derived intermediate voltage through selection of charging/discharging switching operation.
It would have been obvious to one of ordinary skill to provide the multilevel differential switching arrangement of Buter with the series-inductance output filtering taught by Hoyerby because both references concern multilevel PWM switching circuits driving a load, and Hoyerby expressly teaches placing the series inductors and associated capacitances between the switching outputs and the load to suppress the switching-frequency components of the output waveform.
The modification therefore constitutes use of a known output-filter arrangement for its known filtering function in a multilevel PWM switching driver.
With respect to claim 2, Buter expressly teaches:
ground, half supply voltage Vs or supply voltage Vs.
Buter, col. 1, ll. 37–39.
Buter then identifies the capacitive divider as a known circuit for deriving:
“a Voltage that equals half of the Supply Voltage.”
Buter, col. 1, ll. 39–41.
Buter further teaches continuous capacitor interchange to generate the one-half-supply voltage. Buter, col. 1, ll. 43–60.
With respect to claim 3, claim 3 requires the intermediate voltage to be a fraction of the input voltage other than one-half.
Høyerby expressly teaches that the predetermined DC voltage difference need not equal one-half the difference between the first and second DC supplies and that selecting a different value provides a four-level signal.
Hoyerby, col. 3, ll. 23–30.
With respect to claim 6, claim 6 requires the filter arrangement additionally to comprise a shunt capacitance.
Høyerby's output filter includes both a load inductor and a load capacitor. Specifically, Høyerby identifies the first load capacitor 422 and first load inductor and corresponding second load inductor 437 and second load capacitor 423.
Hoyerby, col. 16, ll. 40–60; Fig. 4(b).
The capacitor therefore provides the claimed shunt capacitance associated with the series-inductance output filter.
With respect to claim 12, Buter expressly teaches implementation of the switches of the multilevel driver using MOS transistors (col. 3, ll. 36–40). A conventional MOSFET includes an intrinsic body diode and consequently possesses unidirectional OFF-state current-blocking capability, i.e., it blocks current of one polarity while permitting current of the opposite polarity through the body diode. Thus, implementation of Buter's expressly disclosed MOS transistor switches using conventional MOSFET devices provides the claimed unidirectional current-blocking capability.
With respect to claim 13, Høyerby expressly teaches controller 1103 receiving analog audio input signals. Hoyerby, col. 24, ll. 25–39.
The resulting audio signal is supplied through loop filter 1117 and analog PWM circuit 1115. Hoyerby col. 24, ll. 48–66.
With respect to claim 14, Høyerby's disclosed load is loudspeaker 440.
The patent expressly describes the H-bridge output driver as coupled to a loudspeaker load and identifies the corresponding load/filter components. Hoyerby, col. 16, ll. 40–62; Fig. 4(b).
With respect to claim 15, To the extent claim 15 requires the switching driver, filter arrangement and load as an apparatus, Høyerby's Fig. 4(b) expressly shows the switching output circuitry, series inductors/load capacitors and loudspeaker load as the disclosed system. Hoyerby, Fig. 4(b); col. 16, ll. 40–62.
Claim 16 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 9,515,617 (Hoyerby) in view of U.S. Patent No. 9,246,407 (Schroeder et al.; hereinafter Schroeder).
Høyerby teaches a switching driver having a first output node VA for driving load 440 through a filter arrangement comprising load inductor 438 in series with the load and load capacitor 422 (Fig. 4(b); col. 16, ll. 40–65); first and second supply voltages VS and GND; and a driver switch network SW1–SW4 including flying capacitor 418 coupled between nodes 418a and 418b and precharged to approximately ½VS, thereby providing an intermediate voltage between VS and GND (col. 16, l. 65–col. 17, l. 13; Fig. 4(b)). Høyerby further teaches controlling SW1–SW4 so that output node VA selectively assumes VS, ½VS, or GND (col. 17, ll. 25–48), and controller 1103 and switching-pattern mapping circuit 1119 generate appropriately timed PWM switch-control signals based on an input signal (col. 24, ll. 25–66; col. 25, ll. 1–9; Fig. 11).
Høyerby does not expressly teach selecting the switch states to regulate the intermediate voltage provided by flying capacitor 418.
Schroeder, however, teaches regulating flying-capacitor voltage by selecting among redundant switching states that produce the same output voltage according to whether the flying capacitor requires charging or discharging (col. 3, ll. 33–67; col. 4, ll. 1–10; Table 1). Schroeder specifically teaches that the redundant switching states are employed to balance the flying-capacitor voltages by charging or discharging the capacitors.
It would have been obvious to one of ordinary skill in the art to modify Høyerby's controller to select switch states according to the charging or discharging requirement of flying capacitor 418, as taught by Schroeder, to regulate and maintain Høyerby's intended intermediate capacitor voltage while retaining the desired output voltage level.
With respect to claim 17, claim 17 adds the shunt capacitance.
Høyerby expressly provides the output load capacitor in conjunction with its series load inductor. Hoyerby, col. 16, ll. 50–65; Fig. 4(b).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 3, 6, 8 – 11 and 19 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 7 and 9 - 13 of copending Application No. 18/626995 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because;
Instant claims 1–3 recite substantially the same multilevel switching-driver architecture and intermediate-voltage arrangement of claims 1 and 7 of 18/626995, with additional limitations concerning the output-filter arrangement and/or intermediate-voltage relationship. Instant claim 6 further defines the filter arrangement. The addition of conventional output filtering to the otherwise patentably indistinct switching-driver architecture does not render the claimed subject matter patentably distinct.
Instant Claims 8–11 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9–13 of copending Application No. 18/626,995.
Reference claim 9, depending from claim 1, expressly recites the driver capacitance comprising a driver capacitor connected between first and second capacitor nodes, the first capacitor node being selectively connectable to each of the first and second output nodes and the second capacitor node being connected to a defined reference voltage.
Reference claims 10 and 11 further specify that the defined reference voltage is one of the first and second voltages and, specifically, ground.
Reference claim 12 further requires the driver capacitor to be the only capacitor to which the first and second output nodes may be connected.
Most importantly, reference claim 13, depending from claim 1, expressly recites, for each first and second output node:
a first set of three switches
selectively connecting a first common node to the first switching voltage, intermediate switching voltage, and relevant output node, and another set of three switches selectively connecting a second common node to the second switching voltage, intermediate switching voltage, and relevant output node. Reference claim 13 further requires that, when an output node is connected to the intermediate switching voltage, the relevant switches of both three-switch sets are ON.
Thus, the reference claims expressly claim the common-node/three-switch topology underlying instant claims 8–11 rather than merely describing that topology in the specification.
The additional limitations of instant claims 8–11 constitute particular implementations or operation of the same capacitor-node/common-node switch architecture and do not render those claims patentably distinct from the subject matter of reference claims 9–13.
Claim 19 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 13 of copending Application No. 18/626,995.
Reference claim 1 recites a switching driver having first and second output nodes for providing a differential drive signal to a load; first, second, and intermediate switching voltages; a driver capacitance providing the intermediate switching voltage; a driver switch network selectively connecting the output nodes to the respective switching voltages; and a controller operating the driver switch network in a sequence of switch states based on an input signal while providing voltage regulation of the intermediate voltage.
Reference claim 13, depending from claim 1, further requires, for each output node, a first set of three switches selectively connecting a first common node to the first switching voltage, intermediate switching voltage, and relevant output node, and another set of three switches selectively connecting a second common node to the second switching voltage, intermediate switching voltage, and relevant output node. Reference claim 13 further specifies the switch operation used when the output node is connected to the intermediate switching voltage.
Instant claim 19 recites the same underlying differential multilevel switching-driver architecture together with the common-node/three-switch network claimed in reference claims 1 and 13.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Note the Abstracts and Figs. of the additional references cited on the accompanying 892. Any inquiry concerning this communication or earlier communication from the examiner should be directed to William Deane whose telephone number is 571 - 272 - 7484. The examiner can normally be reached on Monday - FRIDAY from 9:00 A.M. to 5:00 P.M. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Ahmad Matar, can be reached on 571- 272-7488.
The official fax phone number for the organization where this application or proceeding is assigned is 571 -273-8300. However, unofficial faxes can be direct to the examiner's computer at 571 273 -7484.
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19Sep2026
/WILLIAM J DEANE JR/ Primary Examiner, Art Unit 2693
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