The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-9 and 23-31 are presented for examination in this application (19/050,816) filed on June 30, 2026 as claims 10-22 were not elected.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-9 and 23-31 are pending for consideration.
Drawings
The drawings submitted on February 11, 2025 have been considered and accepted.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 23 and 31 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “operable to” as it is unclear what “operable to” refer to and whether the functions being operable are being performed or the intended use is to perform these functions. Claims 1 and 23 further recite second channel interface operable to access one or more of the plurality of memory arrays”, where it is unclear it is the same one or more of the plurality of memory arrays or different.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 23 and 24 are rejected under 35 U.S.C. 103(a) as being disclosed by Lee et al. (US PGPUB 2022/0413768 hereinafter referred to as Lee), and further in view of Kelly et al. (US 7,269,709 hereinafter referred to as Kelly).
As per independent claim 1, Lee discloses a memory device, comprising: a plurality of memory arrays; a first channel interface operable to access one or more of the plurality of memory arrays; a second channel interface operable to access one or more of the plurality of memory arrays [(Paragraphs 0011-0021; FIGs. 1 and 2) wherein FIG. 1 depicts a memory system 100 in which a memory module 105 serves a memory controller 110 in either a two-channel, wide-data mode or a four-channel, narrow-data mode. In either mode, each channel supports independent command and data pathways. The number of available channels can thus be optimized for different numbers of threads in combination with memory capacity and bandwidth. The independent channels also allow secure sharing of memory resources among programs deployed by mutually mistrusting parties. Memory module 105 is a load-reduced, dual inline memory module (LRDIMM) in this embodiment, a printed-circuit board (PCB) 115 with two horizontal rows of memory components 120 on either side. “Dual inline” refers to electrical connections 125 that run along both size of the bottom edge of PCB 115 to form a module connector 130 with two host-side module command ports DCA_A[6:0] and DCA_B[6:0] and four sets of module data ports DQ_A0[39:20], DQ_A1[19:0], DQ_B0[39:20], and DQ_B1[19:0] supporting like-identified links to controller 110, the host in this example. A collection of data buffers 135 communicates data signals between controller 110 and multiple memory components 120. The resulting reduction on the number of data interfaces reduces the load on controller 110 and is responsible for the “load-reduced” naming convention. A registered clock driver (RCD) 140, sometimes called an address-buffer integrated circuit, similarly manages command, address, and clock signals from module command ports DCA_A[6:0] and DCA_B[6:0] to reduce signal loading and distribute command and address signals as needed to collections of memory components 120 via four secondary command/address (CA) ports CA0_A[13:0], CA1_A[13:0], CA0_B[13:0], and CA1_B[13:0] serving like-identified links to memory components 120. Secondary, memory-side command ports CA0_A[13:0] and CA1_A[13:0] are each coupled to five memory components 120, three in one row and two in the other, on each side of PCB 115. The opposite side of PCB 115 is omitted for ease of illustration. Memory-side command ports CA0_B[13:0] and CA1_B[13:0] are each likewise connected to ten memory components each, five on each side of PCB 115, but those too are omitted from FIG. 1 to correspond to the claimed limitation]; and processing circuitry coupled with the plurality of memory arrays, the first channel interface, and the second channel interface, the processing circuitry operable to cause the memory device to: configure the memory device for first operations in a first mode in which the memory device decodes first access commands communicated using one or more first command/address terminals of the first channel interface and decodes second access commands communicated using one or more second command/address terminals of the second channel interface [(Paragraphs 0011-0021; FIGs. 1 and 2) wherein FIG. 2 includes two timing diagrams for command timing in memory system 100 of FIG. 1, a timing diagram 200 of module 105 in the two-channel mode and a timing diagram 205 for module 105 in the four-channel mode. A periodic clock signal CK with clock period 1tCK synchronizes timing for both modes. Beginning with the two-channel mode of diagram 200, controller 110 issues commands to module command port DCA_A[6:0] as a sequence of four seven-bit symbols on successive rising and falling edges of clock signal CK. A primary chip-select signal DCSA_n (“n” for active low) is asserted for one clock period 1tCK, or just tCK. As is well known, CA signals convey command and address signals (e.g., a write command directing that data be written to a specified memory address) and chip-select signals to select one or a set of memory dies, or chips, out of several that share a common data bus. The signals conveyed over module interfaces DCA_A[6:0] and DCSA_n thus specify what is to be done (read or write) with particular addresses in a select set of memory dies within memory components 120. RCD 140 controls memory components 120 on behalf of controller 110 in response to the primary CA and chip-select signals, imposing delays depicted as equivalent and successive time intervals t1 and t2 staggered by one clock period tCK. RCD 140 doubles the width of the CA signals, from seven to fourteen, and issues the wider but otherwise similar commands and addresses as secondary signals CA_A[13:0] (both CA0_A[13:0] and CA1_A[13:0] in FIG. 1) to control a rank of ten memory ICs, one in each of memory components 120. RCD 140 asserts a secondary chip-select signal CSA_n to select the sought-after rank of chips. RCD 140, though not shown in diagram 200, also controls all five data buffers 135 on the left side of module 105 to communicate data of width forty with the selected ten-chip rank. The burst length is 16 bits so access granularity is 640 bits per channel. The second channel, shown to include module CA port DCA_B[6:0] and module data port DQ_B[39:0] in FIG. 1, functions identically to but independent from the other channel. Turning to diagram 205, in the four-channel mode controller 110 issues commands for two secondary CA interfaces CA0_A[13:0] and CA1_A[13:0] using a single module CA port DCA_A[6:0]. Commands to secondary CA port CA0_A[13:0] (CA1_A[13:0]) are conveyed to module 105 via module CA port DCA_A[6:0] as a sequence of four seven-bit symbols on successive rising (falling) edges of clock signal CK. A primary chip-select signal DCSA_n is asserted for half of period tCK for each secondary command. Interleaving commands on module CA interface DCA_A[6:0] halves the CA bandwidth for each channel sharing the same CA links to correspond to the claimed limitation].
Lee does not appear to explicitly disclose configure the memory device for second operations in a second mode in which the memory device decodes third access commands communicated using the one or more first command/address terminals of the first channel interface and the one or more second command/address terminal of the second channel interface.
However, Kelly discloses configure the memory device for second operations in a second mode in which the memory device decodes third access commands communicated using the one or more first command/address terminals of the first channel interface and the one or more second command/address terminal of the second channel interface [(Column 3, lines 15-33 and Column 8, lines 27-47) where the memory controller 14 may receive the transactions, and decode each transaction into a command to access the memory system 24. The memory controller 14 may implement multiple channels to the memory system 24. The memory controller 14 may be configured to gang channels together, and may transfer data to/from the memory system 24 for a command using the ganged combination of channels. With the channels ganged together, more data may be transferred per unit time, and thus the latency to transfer all of the data requested by the command may be relatively low. On the other hand, the memory controller 14 may be configured to operate the channels independently. The independent channels may be used to transfer data for multiple commands concurrently. While each command may be higher latency than if the channels were ganged together, bandwidth utilization may be higher in some embodiments, and thus effective bandwidth may be increased; Each of the channels 54A-54D provides an independent access path to the memory system 24. The channels may be ganged together via operation of the memory controller 14 such that the ganged channels are concurrently used to transfer data for the same command. For example, in FIG. 2, channel 0 and channel 2 (reference numerals 54A and 54C) may be ganged together. Similarly, channel 1 and channel 3 (reference numerals 54B and 54D) may be ganged together. Channels are referred to as "ganged" if at least the data portion of the channels are operated together as if they were one channel. For example, data concurrently transmitted on the ganged channels may be data for the same command. The address and control information on the ganged channels may be the address and control information for the same command. In some embodiments, the address and control information from only one of the channels may be used, in which case the address and control information on the other channels may be a don't care (e.g. may not be driven). On the other hand, address and data information concurrently transmitted on non-ganged channels may be for separate commands to correspond to the claimed limitation].
Lee and Kelly are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kelly before him or her, to modify the device of Lee to include the channel control operations of Kelly because it will enhance memory performance.
The motivation for doing so would be [“ensure that the packets can be written to and read from memory without having to drop packets, or without slowing down the network packet traffic with flow control” (Column 1, lines 35-39 by Kelly)].
Therefore, it would have been obvious to combine Lee and Kelly to obtain the invention as specified in the instant claim.
As per dependent claim 2, Lee discloses wherein the processing circuitry is operable to cause the memory device to: decode the first access commands and the second access commands in the first mode in accordance with a first quantity of clock cycles at the memory device; and decode the third access commands in the second mode in accordance with a second quantity of clock cycles at the memory device that is less than the first quantity of clock cycles [(Paragraphs 0019-0022; FIGs. 1 and 2) where RCD 140 controls memory components 120 on behalf of controller 110 in response to the primary CA and chip-select signals, imposing delays depicted as equivalent and successive time intervals t1 and t2 staggered by one clock period tCK. RCD 140 doubles the width of the CA signals, from seven to fourteen, and issues the wider but otherwise similar commands and addresses as secondary signals CA_A[13:0] (both CA0_A[13:0] and CA1_A[13:0] in FIG. 1) to control a rank of ten memory ICs, one in each of memory components 120. RCD 140 asserts a secondary chip-select signal CSA_n to select the sought-after rank of chips. RCD 140, though not shown in diagram 200, also controls all five data buffers 135 on the left side of module 105 to communicate data of width forty with the selected ten-chip rank. The burst length is 16 bits so access granularity is 640 bits per channel. The second channel, shown to include module CA port DCA_B[6:0] and module data port DQ_B[39:0] in FIG. 1, functions identically to but independent from the other channel. Turning to diagram 205, in the four-channel mode controller 110 issues commands for two secondary CA interfaces CA0_A[13:0] and CA1_A[13:0] using a single module CA port DCA_A[6:0]. Commands to secondary CA port CA0_A[13:0] (CA1_A[13:0]) are conveyed to module 105 via module CA port DCA_A[6:0] as a sequence of four seven-bit symbols on successive rising (falling) edges of clock signal CK. A primary chip-select signal DCSA_n is asserted for half of period tCK for each secondary command. Interleaving commands on module CA interface DCA_A[6:0] halves the CA bandwidth for each channel sharing the same CA links. RCD 140 controls memory components 120 on behalf of controller 110 in response to the module CA and chip-select signals from controller 110. As in the two-channel mode, RCD 140 doubles the CA width, from seven to fourteen, and issues the wider but otherwise similar commands and addresses as secondary signals. In the four-channel mode, however, each of the two types of time-interleaved commands, those conveyed on rising clock edges versus those conveyed on the falling clock edges, are conveyed on respective secondary CA ports CA0_A[13:0] and CA1_A[13:0]. RCD 140 imposes different delays t3 and t4 on each combined pair of primary command signals, where t3 is the sum of t4 and clock period tCK, to provide successive commands on the secondary command interfaces. Having conveyed a command on one secondary CA interface, RCD 140 can present command and address signals on another secondary CA interface after a delay t5 of that is a half clock cycle (tCK/2) shorter than delay t3 to correspond to the claimed limitation].
As for independent claim 23, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 24, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Claims 8 and 30 are rejected under 35 U.S.C. 103(a) as being disclosed by Lee/Kelly, as applied to claims 1 and 23, and further in view of Tak et al. (US 8,654,603 hereinafter referred to as Tak).
As per dependent claim 8, Lee/Kelly discloses the memory device of claim 1.
Lee/Kelly does not appear to explicitly disclose wherein the processing circuitry is operable to cause the memory device to: configure the memory device for the second operations in the second mode based at least in part on an indication of an evaluation condition of the memory device.
However, Tak discloses wherein the processing circuitry is operable to cause the memory device to: configure the memory device for the second operations in the second mode based at least in part on an indication of an evaluation condition of the memory device [(Column 8, lines 38-60; FIGs. 1, 7 and 9) wherein Tak teaches wherein when the test mode signal TM is at a high level, i.e., in the test mode, the pre-active address PA_ADD, the active address A_ADD and the write address W_ADD received through the CA pin are selected and outputted. The pre-active address PA_ADD, the active address A_ADD and the write address W_ADD are sequentially input through the CA pin. On the other hand, when the test mode signal TM is at a low level, i.e., in the normal mode, the command address C_ADD received from the command address storage unit 120 is selected and outputted. Thus, in accordance with an embodiment of the present invention, in the test mode, the address and data are transmitted to the memory using pre-active, active and write commands. The address output unit 320 includes an AND gate AND4 and a latch R. The AND gate AND4 performs an AND operation on the test mode signal TM and the write command WT. When an output of the AND gate AND4 is activated to a high level, the latch R latches an output address of the address selection unit 310 to output the cell array address CA_ADD to the memory to correspond to the claimed limitation].
Lee/Kelly and Tak are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lee/Kelly and Tak before him or her, to modify the device of Lee/Kelly to include the channel interfaces of Tak because it will enhance memory performance.
The motivation for doing so would be [“program code is transmitted from the command decoder 200 directly into the memory without passing through the command code storage unit 110 of the overlay window 100” (Column 6, lines 62-65 by Tak)].
Therefore, it would have been obvious to combine Lee/Kelly and Tak to obtain the invention as specified in the instant claim.
As for dependent claim 30, the applicant is directed to the rejections to claim 8 set forth above, as they are rejected based on the same rationale.
Claims 9 and 31 are rejected under 35 U.S.C. 103(a) as being disclosed by Lee/Kelly, as applied to claims 1 and 23, and further in view of Cho et al. (US PGPUB 2019/0033909 hereinafter referred to as Cho).
As per dependent claim 9, Lee/Kelly discloses the memory device of claim 1.
Lee/Kelly does not appear to explicitly disclose wherein the plurality of memory arrays, the first channel interface, the second channel interface, and the processing circuitry are included in a first semiconductor die, the memory device further comprising a second semiconductor die, the second semiconductor die comprising: a second plurality of memory arrays; a third channel interface operable to access one or more of the second plurality of memory arrays; a fourth channel interface operable to access one or more of the second plurality of memory arrays; and second processing circuitry coupled with the second plurality of memory arrays, the third channel interface, and the fourth channel interface, the second processing circuitry operable to cause the memory device to: configure the memory device for third operations in the first mode in which the memory device decodes fourth access commands communicated using one or more third command/address terminals of the third channel interface and decodes fifth access commands using one or more fourth command/address terminals of the fourth channel interface; and configure the memory device for fourth operations in the second mode in which the memory device decodes sixth access commands communicated using the one or more third command/address terminals of the third channel interface and the one or more fourth command/address terminals of the fourth channel interface.
However, Cho discloses wherein the plurality of memory arrays, the first channel interface, the second channel interface, and the processing circuitry are included in a first semiconductor die, the memory device further comprising a second semiconductor die, the second semiconductor die comprising: a second plurality of memory arrays; a third channel interface operable to access one or more of the second plurality of memory arrays; a fourth channel interface operable to access one or more of the second plurality of memory arrays; and second processing circuitry coupled with the second plurality of memory arrays, the third channel interface, and the fourth channel interface, the second processing circuitry operable to cause the memory device to: configure the memory device for third operations in the first mode in which the memory device decodes fourth access commands communicated using one or more third command/address terminals of the third channel interface and decodes fifth access commands using one or more fourth command/address terminals of the fourth channel interface; and configure the memory device for fourth operations in the second mode in which the memory device decodes sixth access commands communicated using the one or more third command/address terminals of the third channel interface and the one or more fourth command/address terminals of the fourth channel interface [(Paragraphs 0030-0034 and 0047-0050; FIGs. 1, 5 and 6) wherein Cho teaches Figure (FIG. 1 is a block diagram of a memory system 100 according to an embodiment of the inventive concept. Referring to FIG. 1, the memory system 100 generally includes a plurality of memories 120 and a memory controller 140 connected to the plurality of memories 120 via a plurality of channels (e.g., channels CH1, CH2 . . . to CHx—hereafter, collectively referred to as channels CH1 to CHx). In the illustrated embodiment of FIG. 1, each one of the plurality of memories 120 is respectively connected to one of the plurality of channels CH1 to CHx. However, in different embodiments of the inventive concept, two (2) or more memories from the plurality of memories 120 may be connected to a single channel or commonly connected to multiple channels. Hereinafter, the memories commonly connected to the same channel may be referred to as a “memory group”. Here, the plurality of memories 120 may include memories of similar or differing type, operating characteristics, physical form factors, data storage capacity, etc.; FIG. 2 is a block diagram further illustrating in one example the plurality of memories 120 of FIG. 1. Referring to FIG. 2, each of the plurality of memories 120 may include one or more flash memory chip(s) (e.g., NAND-type flash memory, NOR-type flash memory, single level flash memory cells (SLC, multi-level memory cells (MLC), etc.) commonly connected in a flash memory group to one of the plurality of channels CH1 to CHx. The flash memory chips in each flash memory group connected to a respective channel may be controlled (i.e., operated or driven) independently from each other. For example, a first flash memory group 120_1 (e.g., including flash memory chip 11 through flash memory chip 1y) connected to a first channel CH1, and a second flash memory group 120_2 (e.g., including flash memory chip 21 through flash memory chip 2y) connected to a second channel CH2 may independently operated; wherein the first channel interface 142_1 includes the first clock modulator 142_11 receiving the first input clock CLKi1 and modulating the first input clock CLKi1 into the first slave clock CLKs1. As a result and as before, the first Tx/Rx 142_12 is able to communicate first CAD signals via the first channel CH1 synchronously with the first slave clock CLKs1. However, the resulting first slave clock CLKs1 is then passed to the second clock modulator 142_21 as a second input clock CLKi2. Thereafter, the second clock modulator 142_21 may modulate the second input clock CLKi2 to generate the second slave clock CLKs2, and the second Tx/Rx 142_22 will communicate CAD signals via the second channel CH2 synchronously with the second slave clock CLKs2, where the second die of Cho to include the same architecture of Lee/Kelly to correspond to the claimed limitation].
Lee/Kelly and Cho are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lee/Kelly and Cho before him or her, to modify the device of Lee/Kelly to include the channel interfaces of You because it will enhance memory buffering.
The motivation for doing so would be [“memory systems providing improved reliability of operations and method of operating such a memory system” (Paragraph 0002 by Cho)].
Therefore, it would have been obvious to combine Lee/Kelly and Cho to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 3 and 25, but would be allowable if rewritten as independent claims.
The reason for allowance of claim 3 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 3, the limitations of “wherein the processing circuitry is operable to cause the memory device to: decode the second access commands in the first mode based at least in part on latching of the one or more second command/address terminals that is aligned with rising edges of a second clock signal; and decode the third access commands in the second mode based at least in part on latching of the one or more first command/address terminals and the one or more second command/address terminals that is aligned with rising edges and falling edges of a third clock signal”.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Srinivasan et al., US 11,662,939 – teaches Checking Status Of Multiple Memory Dies In A Memory Sub-system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571)270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
