Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1-3, 7-13, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KATAEVA et al (Pub. No.: US 2020/0125936).
3. Regarding independent claim 1, KATAEVA et al teaches an artificial intelligence processing device (Fig. 9) comprising: a substrate (Fig. 2, any semiconductor device would have a substrate); an operation circuit (Fig. 9, #20, Fig. 3) that includes a first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) and a second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) that are provided on the substrate (Fig. 2, any semiconductor device would have a substrate) and have a same structure (see Fig. 3, #24), the first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) and the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) each holding conductance (Fig. 3, G(+) and G(-), paragraph [0047], lines 6-14); and a write circuit (Fig. 9, #31) that rewrites the conductance of the first variable-resistance nonvolatile storage element by applying a first voltage pulse (Fig. 3, paragraph [0047], lines 5-6, V1) having a first voltage (Fig. 3, paragraph [0047], lines 5-6, V1) to the first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example), and rewrites the conductance (Fig. 3, see paragraph [0047]-[0049]) of the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) by applying a second voltage pulse (Fig. 3, paragraph [0047], lines 7-8, V2) having a second voltage (Fig. 3, paragraph [0047], lines 7-8, V2) to the second variable- resistance nonvolatile storage element, the second voltage (Fig. 3, paragraph [0047], lines 7-8, V2) being different (Fig. 3, paragraph [0047]) from the first voltage (Fig. 3, paragraph [0047], lines 5-6, V1).
4 Regarding claim 2, KATAEVA et al teaches the operation circuit (Fig. 9, #20, Fig. 3) is a multiply-accumulate operation circuit (Fig. 9, #20, Fig. 3, #27a, #27b) that performs a multiply-accumulate operation (Fig. 3, #27a, #27b, paragraph [0047]) for which a combined value (see paragraph [0048]) is used as a weight coefficient (Fig. 3, G(+)1, 2, G(-)1, 2), the combined value (see paragraph [0048]) resulting from combining the conductance of the first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) and the conductance of the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example).
5. Regarding claim 3, KATAEVA et al teaches the operation circuit (Fig. 9, #20, Fig. 3) performs the multiply-accumulate operation (Fig. 3, #27a, #27b, paragraph [0047]) by using, as one product, a sum total of a current flowing through the first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) and a current flowing (Fig. 3, paragraph [0048]) through the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example).
6. Regarding claim 7, KATAEVA et al teaches the first variable-resistance nonvolatile storage element (Fig. 3, #23, G(+)1 for example) and the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) are provided in a same layer between two wiring layers (see Fig. 2).
7. Regarding claim 8, KATAEVA et al teaches the first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) is provided in a first layer between two wiring layers (see Fig. 2), and the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) is provided in a second layer between two wiring layers (see Fig. 2), the second layer being different from the first layer (see Fig. 2).
8. Regarding claim 9, KATAEVA et al teaches each of the first variable-resistance nonvolatile storage element (Fig. 3, #23, G(+)1 for example) and the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) includes a first electrode (Fig. 2, #21), a second electrode (Fig. 2, #23), and a variable resistance layer (Fig. 3, #24) between the first electrode and the second electrode (Fig. 2, #21, #23).
9. Regarding claim 10, KATAEVA et al teaches wherein the first electrode (Fig. 2, #21) included in each of the first variable-resistance nonvolatile storage element (Fig. 2, #24) and the second variable-resistance nonvolatile storage element (Fig. 2, #24) is a noble metal electrode (see Fig. 2).
10. Regarding claim 11, KATAEVA et al teaches the first electrode (Fig. 2, #21) included in each of the first variable-resistance nonvolatile storage element (Fig. 2, #24) and the second variable-resistance nonvolatile storage element (Fig. 2, #24) includes at least one of Ir or Pt (Fig. 2, paragraph [0042]).
11. Regarding claim 12, KATAEVA et al teaches a first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) and a second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) that have a same structure (see Fig. 3, #24) and hold, as conductance, a weight coefficient for a multiply-accumulate operation, the weight coefficient writing method comprising: rewriting the conductance of the first variable-resistance nonvolatile storage element (Fig. 3, #23 G(+)1 for example) by applying a first voltage (Fig. 3, paragraph [0047], lines 5-6, V1) pulse (Fig. 3, paragraph [0047], lines 5-6, V1) having a first voltage (Fig. 3, paragraph [0047], lines 5-6, V1) to the first variable-resistance nonvolatile storage element (Fig. 3, #23, G(+)1 for example); and rewriting the conductance of the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) by applying a second voltage (Fig. 3, paragraph [0047], lines 7-8, V2)pulse (Fig. 3, paragraph [0047], lines 7-8, V2) having a second voltage (Fig. 3, paragraph [0047], lines 7-8, V2)to the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) in at least a resistance increasing process, the second voltage (Fig. 3, paragraph [0047], lines 7-8, V2) being different from the first voltage (Fig. 3, paragraph [0047], lines 5-6, V1).
12. Regarding claim 13, KATAEVA et al teaches the rewriting of the conductance of the first variable-resistance nonvolatile storage element (Fig. 3, #23, G(+)1 for example) is executed when the weight coefficient (see Fig. 3, paragraph [0046]-[0047]) is initially set in the artificial intelligence processing device (Fig. 9), and the rewriting of the conductance (Fig. 3, paragraph [0048]) of the second variable-resistance nonvolatile storage element (Fig. 3, #24, G(-)1 for example) is executed when the weight coefficient (Fig. 3, paragraph [0047]) is updated by training the artificial intelligence processing device (Fig. 9).
Allowable Subject Matter
13. Claims 4-6, 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. With respect to claim 4, there is no teaching, suggestion, or motivation for combination in the prior art to the conductance of the first variable-resistance nonvolatile storage element discontinuously changes when the first voltage pulseis repeatedly applied, and the conductance of the second variable- resistance nonvolatile storage element continuously changes when the second voltage pulse is repeatedly applied.
15. With respect to claim 5, there is no teaching, suggestion, or motivation for combination in the prior art to the first variable-resistance nonvolatile storage element has holding capability higher than holding capability of the second variable-resistance nonvolatile storage element, and the second variable-resistance nonvolatile storage element has rewrite durability higher than rewrite durability of the first variable- resistance nonvolatile storage element.
16. With respect to claim 6, 15, there is no teaching, suggestion, or motivation for combination in the prior art to the second voltage in the resistance increasing process is at most 0.71 times the first voltage in the resistance increasing process.
17. With respect to claim 14, there is no teaching, suggestion, or motivation for combination in the prior art to the first variable-resistance nonvolatile storage element is included in a first artificial intelligence region for using the weight coefficient for artificial intelligence processing as-is in transfer learning or reinforcement learning, the weight coefficient already existing, the second variable-resistance nonvolatile storage element is included in a second artificial intelligence region for updating the weight coefficient by new training in the transfer learning or the reinforcement learning, the rewriting of the conductance of the first variable-resistance nonvolatile storage element is executed when the weight coefficient is written in the first artificial intelligence region, and the rewriting of the conductance of the second variable- resistance nonvolatile storage element is executed when the weight coefficient is updated in the second artificial intelligence region.
Conclusion
18. the prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Yin et al (US Patent 11,107,527).
Yin et al (US Patent 11,107,527) shows a 1T2R structure.
19. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
08/28/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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