DETAILED ACTION
This Non Final Office Action is in response to Application filed on 02/11/2025. Claims 1-20 filed on 02/11/2025 are being considered on the merits.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/11/2025 have been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly an initialed and dated copy of Applicant's IDS form 1449 filed 02/11/2025 are attached to the instant Office action.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Figure. 1B, element 118 is not mentioned in the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 8, 12, 13, 14, 16-17 and 19 are objected to because of the following informalities:
Claim 13 recites “cannot”, which is a non-definitive term. Examiner recommends replacing “cannot” with “does not”
Claim 14, recites “buffer ,”, which has an extra space.
Claim 16, states “databases are switch between.” It should state “databases are switched between.”
Claim 8 recites “program counters”, should be “the program counters”.
Claim 12 recites “a first level of delay” should be “the first level of delay”.
Claim 16 recites “program counters”, should be “the program counters”.
Claim 17 recites “the active squashed processor database and the inactive squashed processor database”, should be “the active squashed processor instruction database; and the inactive squashed processor instruction database”.
Claim 19 recites “the second threshold and a second level of delay is initiated when the counter is equal to or greater than a second threshold, the second threshold”, should recite “a second threshold and a second level of delay is initiated when the counter is equal to or greater than a second threshold, the second threshold”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the
claimed invention is not identically disclosed as set forth in section 102, if the
differences between the claimed invention and the prior art are such that the
claimed invention as a whole would have been obvious before the effective filing
date of the claimed invention to a person having ordinary skill in the art to which
the claimed invention pertains. Patentability shall not be negated by the manner
in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at
issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating
obviousness or nonobviousness.
Claims 1-5, 10, 11, 13, 14, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sakalis et al (Efficient Invisible Speculative Execution through Selective Delay and Value Prediction) and further in view of Gupta et al (WO 2019140274 A1).
Regarding claim 1, Sakalis teaches a method for mitigating micro-architectural attacks in a processing system, the method comprising delaying speculative execution on the processing system (We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3).
Sakalis does not explicitly teach a method for mitigating micro-architectural replay attacks in a processing system. Delaying speculative execution on the processing system of a set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack. Emphasis in italic.
Gupta discloses mitigating micro-architectural replay attacks, the method comprising delaying speculative execution on the processing system of a set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack (The architectural changes caused by these instructions is discarded, but their microarchitectural footprint in the cache is not. ……….he can now recover the victim’s bit by probing the access latency of this memory location. While this attack can be repeated to leak arbitrary bits from arbitrary registers……..One mitigation approach of the present invention for this variant is as follows; [00160] Lines 8-14, [00161] and [0208 “For example, in the case of the“if-then” code block 418, the security platform 130 inserts to the sequence of instructions a memory barrier instruction (e.g., fence instruction) that causes the speculative execution engine to enforce an ordering constraint on memory operations issued before and after the memory barrier instruction.”, [0209] “With the inserted instruction, the speculative execution engine cannot reorder the execution of the instructions in the instruction pipeline 112. Thus, the speculative execution engine must wait to execute a later instruction until the previous instruction ahead of the later instruction is executed. ”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis to incorporate the teachings of Gupta by providing a way to mitigate micro-architectural replay attacks in a processing system and delaying speculative execution on the processing system of a set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack. This will prevent an attacker form capturing, saving and modifying packets. Their ability to capture packets will allow them to impersonate a user to gain access to a system. System owners and users will be protected from data leaks and ransom attacks which would result in losing revenue.
Regarding claim 2, Sakalis in view of Gupta teaches the method of claim 1, wherein the method further comprises…of the set of processor instructions (load instructions. The statistics have been gathered over applications from the SPEC CPU 2006 [49] benchmark suite; Page 725, Col. 2, Paragraph 3, Lines 2-4) interleaved with misspeculation and squashing of the set of processor instructions (If a misspeculation is detected, the instructions following the misspeculation point—also referred to as transient instructions—are squashed and execution is restarted from the misspeculation point.; Page 724, Col. 2, Paragraph 4, Lines 4-6).
Sakalis does not explicitly teach the method further comprises detecting repeating speculative execution.
Gupta teaches the method further comprises detecting repeating speculative execution (Using the monitoring instructions, as an application executes, the method 191 analyzes and identifies 502 a set of application instructions that perform a repeat operation; [0063], Lines 4-6).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis to incorporate the teachings of Gupta by providing a way to detect repeating speculative execution. Detecting repeating speculative execution before the attacker gains access will allow the system owners to implement defensive actions while or before the attach happens. This will prevent an attacker form capturing, saving and modifying packets. Their ability to capture packets will allow them to impersonate a user to gain access to a system. System owners and users will be protected from data leaks and ransom attacks which would result in losing revenue.
Regarding claim 3, Sakalis in view of Gupta teaches the method of claim 1, wherein the set of processor instructions (Sakalis: load instructions. The statistics have been gathered over applications from the SPEC CPU 2006 [49] benchmark suite; Page 725, Col. 2, Paragraph 3, Lines 2-4) comprise side channel instructions (Sakalis: shadowed instructions; Page 725, Col. 1, Paragraph 1, Lines 1-2, Gupta further discloses application instructions; [0063], Line 5, motivation in clam 1 apply).
Regarding claim 4, Sakalis in view of Gupta teaches the method of claim 1, wherein delaying speculative execution (flushing the resources of the spy or partition the involved processes; Fig. 2, defense actuator 230, [0045], Lines 7-8) further comprises:
maintaining a reorder buffer (reorder buffer; Page 724, Col. 2, Paragraph 2, Line 5) comprising the set of processor instructions (load instructions. The statistics have been gathered over applications from the SPEC CPU 2006 [49] benchmark suite; Page 725, Col. 2, Paragraph 3, Lines 2-4)…that can cause misspeculation and squashing of the set of processor instructions (If a misspeculation is detected, the instructions following the misspeculation point—also referred to as transient instructions—are squashed and execution is restarted from the misspeculation point.; Page 724, Col. 2, Paragraph 4, Lines 4-6), each processor instruction in the set of processor instructions comprising an associated unique program counter (head and tail pointers of the reorder buffer,; Page 728, Col. 2, Paragraph 3, Line 1) in the reorder buffer; and placing the program counter…in a handle queue (When the second load (LD2) enters the ROB the SB is no longer empty and the load therefore shadowed. It is still entered into the load queue but it is marked as speculative; Page 729, Col. 1, Lines 4-6).
Sakalis does not explicitly teach the set of processor instructions comprising dynamic instructions.
Gupta teaches the set of processor instructions comprising side channel instructions (application instructions; [0063], Line 5) and dynamic instructions (monitoring instructions; [0063], Line 4).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis to incorporate the teachings of Gupta by set of processor instructions comprising side channel instructions and dynamic instructions. Having both side channel instructions and dynamic instructions will allow the processor to insert incoming instructions into a system that will determine if the current instructions are a part of repeating attack. Making this determination will allow the system owners to implement defensive actions while or before the attach happens. This will prevent an attacker form capturing packets, saving and modifying them then using them to impersonate a user to gain access to a system. System owners and users will be protected from data leaks and ransom attacks which would result in losing revenue.
Regarding claim 5, Sakalis in view of Gupta teaches the method of claim 4, wherein: the set of processor instructions (Sakalis: all instructions are considered speculatively executed until they reach the head of the reorder buffer; Page 724, Col. 2, Paragraph 4, Lines 7-8) in the reorder buffer (Sakalis: reorder buffer; Page 724, Col. 2, Paragraph 2, Line 5) comprises squashed processor instructions (the instructions that follow it will have to be squashed; Page 724, Col. 2 and Paragraph 4, Line 17 and Page 725, Col. 1 and Paragraph 1, Line 1; shadowed instructions; Page 725, Col. 1, Paragraph 1, Line 2); and
delaying speculative execution (Sakalis: We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3) further comprises:
storing program counters for the squashed processor instructions in at least one squashed processor instruction database (Sakalis: the second load (LD2) enters the ROB ……..It is still entered into the load queue but it is marked as speculative (d)…….There, its index in the load queue (e); Page 729, Col. 1, Lines 4-8); and
tagging the at least one squashed processor instruction database with a youngest dynamic instruction from the reorder buffer at a time when the program counters are stored (Sakalis: the youngest shadow-casting instruction (identified by SB-Tail minus one) (f) are marked; Page 729, Col. 1, Lines 8-10; Gupta: monitoring instructions; [0063], Line 4).
Regarding claim 10, Sakalis in view of Gupta teaches the method of claim 5, wherein the method further comprises only executing processor instructions not contained in any squashed processor instruction database (Sakalis: all instructions are considered speculatively executed until they reach the head of the reorder buffer (ROB)…… instructions with potential to cause a misspeculation cast a speculative shadow to all the instructions that follow……the instructions that follow it will have to be squashed.; Page 724, Col. 2, Paragraph 4, Lines 7-8, 13-15 and 17; Page 725, Col. 1, Paragraph 1, Line 1).
Regarding claim 11, Sakalis in view of Gupta teaches the method of claim 4, wherein delaying speculative execution (We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3) further comprises:
detecting a new misspeculation and squashing of the set of processor instructions (instructions with potential to cause a misspeculation cast a speculative shadow to all the instructions that follow……the instructions that follow it will have to be squashed.; Page 724, Col. 2, Paragraph 4, Lines 3-15 and 17; Page 725, Col. 1, Paragraph 1, Line 1);
incrementing the counter (queried in parallel; Page 727, Col. 1, Paragraph 3, Line 11).
Sakalis does not explicitly teach identifying a threshold number of squashes of the set processor instructions before initiating a given level of delay in speculative execution of the set of processor instructions; maintaining a counter of a number of squashes of the set of processor instructions; and initiating the given level of delay in the speculative execution of the set of processor instructions when the counter is equal to or greater than the threshold.
Gupta teaches identifying a threshold number of squashes of the set processor instructions before initiating a given level of delay in speculative execution of the set of processor instructions; maintaining a counter of a number of squashes of the set of processor instructions (The method 193 of FIG. 1E may further track and maintain a count based on how many times indirect branch transitions associated to the victim process on a given thread has occurred, which allows the method 193 to determine if the branch transition took place speculatively or not.; [00135] Lines 3-6; If it does not, then a mis-speculation has occurred, and the speculatively executed instructions must be squashed; [00130] Lines 15-16); and
initiating the given level of delay in the speculative execution of the set of processor instructions when the counter is equal to or greater than the threshold (If the count exceeds a threshold, the method 194 takes 535 a protective action, such as terminates the attacker process, moves the attacker process to a quarantine area; [0067] Lines 6-7).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis to incorporate the teachings of Gupta by providing a way to identify a threshold number of squashes. Having a threshold number would allow the system to further analyze the incoming instruction. It will allow the system to determine on whether or not to take mitigating action. It will prevent system owners from losing revenue from potential attacks and can save money on security upgrades after being compromised.
Regarding claim 13, Sakalis in view of Gupta teaches the method of claim 5, wherein delaying speculative execution (Sakalis: We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3) further comprises determining that a given instruction in the instructions in the reorder buffer (Sakalis: reorder buffer; Page 724, Col. 2, Paragraph 2, Line 5) is non-speculative by determining that the given instruction cannot cause misspeculation and squashing of any other processor instruction in the set of processor instructions and that the given dynamic instruction cannot be squashed by any other instruction in the reorder buffer (Sakalis: we assume that interrupts can be delayed until there are no shadowed loads preceding them; Page 725, Col. 2, Paragraph 2, Lines 2-3; As soon as the condition and the branch target are known, the speculation can be verified and the shadow is lifted; Page 725, Col. 1, Paragraph 1, Lines 2-4).
Sakalis does not disclose dynamic instructions, Gupta discloses dynamic instructions, see rationale and motivation in claim 4.
Regarding claim 14, Sakalis teaches a processing system capable of mitigating micro-architectural attacks in the processing system, the processing system comprising:
a processor to execute processor instructions from a computer program executing on the processing system (Sakalis We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3, load instructions. The statistics have been gathered over applications from the SPEC CPU 2006 [49] benchmark suite; Page 725, Col. 2, Paragraph 3, Lines 2-4);
a reorder buffer (reorder buffer; Page 724, Col. 2, Paragraph 2, Line 5),the reorder buffer comprising a set of processor instructions (shadowed instructions; Page 725, Col. 1, Paragraph 1, Lines 1-2), that can cause misspeculation and squashing of the set of processor instructions (If a misspeculation is detected, the instructions following the misspeculation point—also referred to as transient instructions—are squashed and execution is restarted from the misspeculation point.; Page 724, Col. 2, Paragraph 4, Lines 4-6), each processor instruction in the set of processor instructions comprising an associated unique program counter in the reorder buffer (The ROB, release queue, and load queue are also assumed to be implemented as circular buffers such that an entry of these structures can always be identified by its index2; Page 728, Col. 1 and 2, Paragraph 2, Lines 5-8);
a handle queue (The ROB, release queue, and load; Page 728, Col. 1 and 2, Paragraph 2, Lines 5-6) in communication with the processor, the handle queue comprising the program counter for each instruction in the reorder buffer (The ROB, release queue, and load queue are also assumed to be implemented as circular buffers such that an entry of these structures can always be identified by its index2; Page 728, Col. 1 and 2, Paragraph 2, Lines 5-8); and
at least one squashed processor instruction database for storing program counters for squashed processor instructions in the reorder buffer (the second load (LD2) enters the ROB ……..It is still entered into the load queue but it is marked as speculative (d)…….There, its index in the load queue (e); Page 729, Col. 1, Lines 4-8);
wherein the processor only executes processor instructions not contained in the squashed processor instruction database (all instructions are considered speculatively executed until they reach the head of the reorder buffer (ROB)…… instructions with potential to cause a misspeculation cast a speculative shadow to all the instructions that follow……the instructions that follow it will have to be squashed.; Page 724, Col. 2, Paragraph 4, Lines 7-8, 13-15 and 17; Page 725, Col. 1, Paragraph 1, Line 1) to delay speculative execution on the processing system of the set of processor instructions (We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3).
Sakalis does not explicitly teach a processing system capable of mitigating micro-architectural replay attacks in the processing system. A set of processor instructions comprising side channel instructions and dynamic instructions; wherein the processor only executes processor instructions not contained in the squashed processor instruction database to delay speculative execution on the processing system of the set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack.
Gupta teaches a processing system capable of mitigating micro-architectural replay attacks in the processing system (The architectural changes caused by these instructions is discarded, but their microarchitectural footprint in the cache is not…he can now recover the victim’s bit by probing the access latency of this memory location. While this attack can be repeated to leak arbitrary bits from arbitrary registers……..One mitigation approach of the present invention for this variant is as follows; [00160] Lines 8-14 [00161] Line 1). A set of processor instructions comprising side channel instructions (application instructions; [0063], Line 5) and dynamic instructions (monitoring instructions; [0063], Line 4). Delay speculative execution on the processing system of the set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack (Using the monitoring instructions, as an application executes, the method 191 analyzes and identifies 502 a set of application instructions that perform a repeat operation…….the method 191 adds 503 a memory barrier instruction that causes the speculative execution engine to enforce an ordering constraint on memory operations issued before and after the memory barrier instruction, such as a FENCE (x86) instruction; [0063], Lines 4-15).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis to incorporate the teachings of Gupta of a processing system capable of mitigating micro-architectural replay attacks in the processing system. A set of processor instructions comprising side channel instructions and dynamic instructions; wherein the processor only executes processor instructions not contained in the squashed processor instruction database to delay speculative execution on the processing system of the set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack. This will prevent an attacker form capturing, saving and modifying packets. Their ability to capture packets will allow them to impersonate a user to gain access to a system. Having both side channel instructions and dynamic instructions will allow the processor to insert incoming instructions into a system that will determine if the current instructions are a part of repeating attack. Making this determination will allow the system owners to implement defensive actions while or before the attack happens.
Regarding claim 18, Sakalis teaches a processing system capable of mitigating micro-architectural attacks in the processing system (load instructions; Page 725, Col. 2, Paragraph 3, Line 2), the processing system comprising: a processor to execute processor instructions from a computer program executing on the processing system (Sakalis We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3, load instructions. The statistics have been gathered over applications from the SPEC CPU 2006 [49] benchmark suite; Page 725, Col. 2, Paragraph 3, Lines 2-4);
a reorder buffer (reorder buffer; Page 724, Col. 2, Paragraph 2, Line 5), the reorder buffer comprising a set of processor instructions (shadowed instructions; Page 725, Col. 1, Paragraph 1, Lines 1-2), instructions that can cause misspeculation and squashing of the set of processor instructions (If a misspeculation is detected, the instructions following the misspeculation point—also referred to as transient instructions—are squashed and execution is restarted from the misspeculation point.; Page 724, Col. 2, Paragraph 4, Lines 4-6),
each processor instruction in the set of processor instructions comprising an associated unique program counter (head and tail pointers of the reorder buffer; Page 728, Col. 2, Paragraph 3, Line 1) in the reorder buffer; a handle queue (The ROB, release queue, and load; Page 728, Col. 1 and 2, Paragraph 2, Lines 5-6) in communication with the processor, the handle queue comprising the program counter for each instruction in the reorder buffer (The ROB, release queue, and load queue are also assumed to be implemented as circular buffers such that an entry of these structures can always be identified by its index2; Page 728, Col. 1 and 2, Paragraph 2, Lines 5-8).
Sakalis does not disclose the below limitation.
Gupta teaches a processing system capable of mitigating micro-architectural replay attacks in the processing system (The architectural changes caused by these instructions is discarded, but their microarchitectural footprint in the cache is not…he can now recover the victim’s bit by probing the access latency of this memory location. While this attack can be repeated to leak arbitrary bits from arbitrary registers…One mitigation approach of the present invention for this variant is as follows; [00160] Lines 8-14, [00161] Line 1), the set of processor instructions comprising side channel instructions (application instructions; [0063], Line 5) and dynamic instructions (monitoring instructions; [0063], Line 4). A counter containing a number of squashes of the set of processor instructions that have occurred (The method 193 of FIG. 1E may further track and maintain a count based on how many times indirect branch transitions associated to the victim process on a given thread has occurred, which allows the method 193 to determine if the branch transition took place speculatively or not.; [00135] Lines 3-6; If it does not, then a mis-speculation has occurred, and the speculatively executed instructions must be squashed; [00130] Lines 15-16);
wherein a given level of delay in the speculative execution of the set of processor instructions is initiated when the counter is equal to or greater than a predefined threshold to delay speculative execution (If the count exceeds a threshold, the method 194 takes 535 a protective action, such as terminates the attacker process, moves the attacker process to a quarantine area; [0067] Lines 6-7; Fig. 1F, block 535; If the count exceeds a threshold, the method 194 takes 535 a protective action;) on the processing system of the set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack (Using the monitoring instructions, as an application executes, the method 191 analyzes and identifies 502 a set of application instructions that perform a repeat operation…….the method 191 adds 503 a memory barrier instruction that causes the speculative execution engine to enforce an ordering constraint on memory operations issued before and after the memory barrier instruction, such as a FENCE (x86) instruction; [0063], Lines 4-15).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis to incorporate the teachings of Gupta by providing a processing system capable of mitigating micro-architectural replay attacks in the processing system, the set of processor instructions comprising side channel instructions and dynamic instructions, a counter containing a number of squashes of the set of processor instructions that have occurred; wherein a given level of delay in the speculative execution of the set of processor instructions is initiated when the counter is equal to or greater than a predefined threshold to delay speculative execution on the processing system of the set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack. This will prevent an attacker form capturing, saving and modifying packets. Their ability to capture packets will allow them to impersonate a user to gain access to a system. Having dynamic instructions will allow the processor to insert incoming instructions into a system that will determine if the current instructions are a part of repeating attack. Making this determination will allow the system owners to implement defensive actions while or before the attach happens. It will prevent system owners from losing revenue from potential attacks and can save money on security upgrades after being compromised.
Regarding claim 20, Sakalis in view of Gupta teaches the processing system of claim 18, wherein the processing system (Sakalis: the youngest shadow-casting instruction; Page 728, Col. 1, Paragraph 1, Line 8; Gupta - monitoring instructions; [0063], Line 4) further comprises a youngest unresolved dynamic instruction register comprising a uniquely identifying dynamic instance of the program counter associated with a youngest dynamic instruction in the handle queue (Sakalis: Fig. 1; the youngest shadow-casting instruction (identified by SB-Tail minus one) (f) are marked.; Page 729, Col. 1, Paragraph 2, Lines 5-7; Gupta - monitoring instructions; [0063], Line 4).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sakalis et al (Efficient Invisible Speculative Execution through Selective Delay and Value Prediction) and further in view of Gupta et al (WO 2019140274 A1) and further in view of Awad (US 20190394021 A1).
Regarding claim 6, Sakalis in view of Gupta teaches the method of claim 5.
Sakalis, in view of Gupta, does not explicitly teach storing the program counters comprises storing hash values of the program counters.
Awad discloses wherein storing the program counters comprises storing hash values of the program counters (Awad Fig. 8; shows hash values being stored comprising of counters).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Awad by storing the program counters comprises storing hash values of the program counters. Storing program counters will allow the system to facilitate faster execution of instructions leading to improved performance. This will allow data to be available to system users without any delay.
Claims 7 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Sakalis et al (Efficient Invisible Speculative Execution through Selective Delay and Value Prediction) and further in view of Gupta et al (WO 2019140274 A1) and further in view of Thornewell et al (US 11019022 B1).
Regarding claim 7, Sakalis in view of Gupta teaches the method of claim 5, wherein the at least one squashed processor instruction database (Sakalis: If a misspeculation is detected, the instructions following the misspeculation point……are squashed; Page 724, Col. 2, Paragraph 4, Lines 4-6; There, its index in the load queue (e); Page 729, Col. 1, Line 8).
Sakalis in view of Gupta does not explicitly teach wherein the at least one…database comprises a Bloom filter.
Thornewell teaches wherein the at least one…database comprises a Bloom filter (If all of the corresponding bits are set, the test value has been previously stored in the Bloom filter, and the DNS response is likely to be legitimate; Col. 16, Lines 45-47).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Thornewell wherein the at least one squashed processor instruction database comprises a Bloom filter. Incorporating a Bloom filter will drastically reduce or completely eliminate the number of false negatives when detecting relay attacks. Resulting in the increased reliability of the prevention system.
Regarding claim 15, Sakalis in view of Gupta teaches the processing system of claim 14, wherein the at least one squashed processor instruction (Sakalis: If a misspeculation is detected, the instructions following the misspeculation point……are squashed; Page 724, Col. 2, Paragraph 4, Lines 4-6; There, its index in the load queue (e); Page 729, Col. 1, Line 8).
Sakalis in view of Gupta does not explicitly teach wherein the at least one…database comprises a Bloom filter.
Thornewell teaches wherein the at least one…database comprises a Bloom filter (If all of the corresponding bits are set, the test value has been previously stored in the Bloom filter, and the DNS response is likely to be legitimate; Col. 16, Lines 45-47).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Thornewell wherein the at least one…database comprises a Bloom filter. Incorporating a Bloom filter will drastically reduce or completely eliminate the number of false negatives when detecting relay attacks. Resulting in the increased reliability of the prevention system.
Claims 8 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Sakalis et al (Efficient Invisible Speculative Execution through Selective Delay and Value Prediction) and further in view of Gupta et al (WO 2019140274 A1) and further in view of Awad (US 20190394021 A1) and Lv et al (US 10791143 B1).
Regarding claim 8, Sakalis in view of Gupta teaches the method of claim 5.
wherein storing program counters (Sakalis: head and tail pointers of the reorder buffer,; Page 728, Col. 2, Paragraph 3, Line 1) for the squashed processor instructions (Sakalis: the instructions that follow it will have to be squashed; Page 724, Col. 2 and Paragraph 4, Line 17 and Page 725, Col. 1 and Paragraph 1, Line 1; shadowed instructions; Page 725, Col. 1, Paragraph 1, Line 2).
Sakalis in view of Gupta does not explicitly teach the below limitations.
Awad teaches storing program counters for the instructions in two instruction databases (provides counters 154 configured to be loaded in the counter cache 116; [0059] Lines 3-4; the MT cache 124 may be reconstructed with the recovered counter values; [0065] Lines 1-3); designating at a given time one squashed processor instruction database as an active squashed processor instruction database and one squashed processor instruction database as an inactive squashed processor instruction database (counter cache is “used in the encryption operation;” [0059] Lines 6-7; MT cache is used in the crash/attack recovery module 146; [0064] Line 8); inserting, upon detection of an additional squash, program counters associated with squashed processor instructions in the additional squash into the active squashed processor instruction database (provides counters 154 configured to be loaded in the counter cache 116; [0059] Lines 3-4; the MT cache 124 may be reconstructed with the recovered counter values; [0065] Lines 1-3). switching the squashed processor instruction databases between the active squashed processor instruction database and the inactive squashed processor instruction database periodically (Over time, the memory space in Section A can fill up with transaction information.…….Section A (initially the working section in the current example) will cease to be the working section and will become the backup section. At the same time, Section B will cease to be the backup section and will become the working section; Col. 9 Lines 28-36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis in view of Gupta to incorporate the teaching of Awad to utilize the above feature, with the motivation of performing attack recovery, as recognized by (Awad [0064]).
Awad does not explicitly teach the below limitations.
Lv teaches switching the squashed processor instruction databases between the active squashed processor instruction database and the inactive squashed processor instruction database periodically (Over time, the memory space in Section A can fill up with transaction information.…….Section A (initially the working section in the current example) will cease to be the working section and will become the backup section. At the same time, Section B will cease to be the backup section and will become the working section; Col. 9 Lines 28-36).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Awad and Lv storing program counters for the squashed processor instructions in two squashed processor instruction databases; designating at a given time one squashed processor instruction database as an active squashed processor instruction database and one squashed processor instruction database as an inactive squashed processor instruction database; inserting, upon detection of an additional squash, program counters associated with squashed processor instructions in the additional squash into the active squashed processor instruction database; and switching the squashed processor instruction databases between the active squashed processor instruction database and the inactive squashed processor instruction database periodically. Storing program counters will allow the system to facilitate faster execution of instructions leading to improved performance. This will allow data to be available to system users without any delay.
Regarding claim 16, Sakalis in view of Gupta teaches the processing system of claim 14, further comprising squashed processor instructions (Sakalis: the instructions that follow it will have to be squashed; Page 724, Col. 2 and Paragraph 4, Line 17 and Page 725, Col. 1 and Paragraph 1, Line 1; shadowed instructions; Page 725, Col. 1, Paragraph 1, Line 2).
Sakalis in view of Gupta does not explicitly teach the below limitations.
Awad teaches two instruction databases, the two instruction databases comprising (provides counters 154 configured to be loaded in the counter cache 116; [0059] Lines 3-4; the MT cache 124 may be reconstructed with the recovered counter values; [0065] Lines 1-3):
an active instruction database; and an inactive instruction database (counter cache is “used in the encryption operation;” [0059] Lines 6-7; MT cache is used in the crash/attack recovery module 146; [0064] Line 8), program counters associated with processor instructions in the reorder buffer that have been squashed are inserted into the active instruction database upon detection of a squash (provides counters 154 configured to be loaded in the counter cache 116; [0059] Lines 3-4; the MT cache 124 may be reconstructed with the recovered counter values; [0065] Lines 1-3); wherein the instruction databases are switch between the active instruction database and the inactive instruction database periodically (counter cache is “used in the encryption operation;” [0059] Lines 6-7; MT cache is used in the “crash/attack recovery module 146”; [0064] Line 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis in view of Gupta to incorporate the teaching of Awad to utilize the above feature, with the motivation of performing attack recovery, as recognized by (Awad [0064]).
Awad does not explicitly teach the below limitations.
Lv teaches wherein the instruction databases are switch between the active instruction database and the inactive instruction database periodically (Over time, the memory space in Section A can fill up with transaction information.…….Section A (initially the working section in the current example) will cease to be the working section and will become the backup section. At the same time, Section B will cease to be the backup section and will become the working section; Col. 9 Lines 28-36).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Awad and Lv of two instruction databases. Having two instruction databases that switch periodically will allow the instructions that are not a part of a relay attack to process normally without delay. Resulting in reliable system performance while remaining secure.
Claims 12 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Sakalis et al (Efficient Invisible Speculative Execution through Selective Delay and Value Prediction) and further in view of Gupta et al (WO 2019140274 A1) and further in view of Sadasivam et al (US 10884749 B2) and Michalak et al (US 20080046692 A1).
Regarding claim 12, Sakalis in view of Gupta teaches the method of claim 11, wherein: the first level of delay delays only persistent microarchitectural state side channel instructions (Sakalis: We delay speculative loads until they are non-speculative, preventing any speculative side-effects from happening; Page 724, Col. 2, Paragraph 2, Lines 1-3), and the second level of delay delays all side channel instructions (Sakalis: instructions with potential to cause a misspeculation cast a speculative shadow to all the instructions that follow……the instructions that follow it will have to be squashed.; Page 724, Col. 2, Paragraph 4, Lines 3-15 and 17; Page 725, Col. 1, Paragraph 1, Line 1).
Sakalis in view of Gupta does not explicitly teach the below limitations.
Sadasivam teaches identifying the threshold number of squashes (there are multiple cache pollution ratio thresholds; Col. 5, Lines 26-27); comprises:
identifying a first threshold for a first level of delay (where L1 represents a first cache; Col. 5, Lines 30-31); and identifying a second threshold for a second level of delay (L2 represents a second cache; Col. 5, Line 31); and initiating the given level of delay further comprises:
initiating a first level of delay when the counter is equal to or greater than the
first threshold and less than the second threshold; and initiating the second level of delay when the counter is equal to or greater than the second threshold (if the cache pollution ratio is higher than the threshold a False-ID flag is set in the load instructions.; Col. 5, Lines 61-62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis in view of Gupta to incorporate the teaching of Sadasivam to utilize the above feature, with the motivation of controlling speculative demand loads, as recognized by (Sadasivam Abstract).
Sadasivam does not explicitly teach the below limitation.
Michalak teaches the second level of delay stricter than the first level of delay ([0012] Lines 1-4; Processor instruction execution may be controlled by determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions. Execution of the sets of instructions is delayed based on the corresponding delay value; [0022] Lines 21-23; highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay; [0034] Lines 13-15; The more speculative an instruction, the greater the delay that may be assigned to the instruction and vice-versa.)
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Sadasivam and Michalak by providing a way to identify a threshold number of squashes. Having a first and second threshold value would allow the system to capture all incoming instructions while allowing the normal request to process regularly through the system. It will allow the system to determine on whether or not to take mitigating action. This approach will prevent any system slowdowns or delays. Having a second level of delay that is stricter than the first, it will prevent a path to be incorrectly predicted, often referred to as a branch misprediction. When a branch misprediction occurs, all instructions in the mispredicted path are discarded or flushed. Providing this solution will ensure that the power consumption is not adversely affected. It will prevent system owners from losing revenue from potential attacks and can save money on security upgrades after being compromised.
Regarding claim 19, Sakalis, in view of Gupta, teaches the processing system of claim 18.
Sakalis, in view of Gupta, does not explicitly teach the below limitations.
Sadasivam teaches wherein a first level of delay is initiated when the counter is equal to or greater than a first threshold and less than the second threshold and a second level of delay is initiated when the counter is equal to or greater than a second threshold, the second threshold greater than the first threshold (if the cache pollution ratio is higher than the threshold a False-ID flag is set in the load instructions.; Col. 5, Lines 61-62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis in view of Gupta to incorporate the teaching of Sadasivam to utilize the above feature, with the motivation of controlling speculative demand loads, as recognized by (Sadasivam Abstract).
Sadasivam does not explicitly teach the below limitation.
Michalak teaches the second level of delay stricter than the first level of delay ([0012] Lines 1-4; Processor instruction execution may be controlled by determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions. Execution of the sets of instructions is delayed based on the corresponding delay value; [0022] Lines 21-23; highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay; [0034] Lines 13-15; The more speculative an instruction, the greater the delay that may be assigned to the instruction and vice-versa.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakalis, in view of Gupta, to incorporate the teachings of Sadasivam and Michalak by providing a way to identify a threshold number of squashes. Having a first and second threshold value would allow the system to capture all incoming instructions while allowing the normal request to process regularly through the system. It will allow the system to determine on whether or not to take mitigating action. This approach will prevent any system slowdowns or delays. Having a second level of delay that is stricter than the first, it will prevent a path to be incorrectly predicted, often referred to as a branch misprediction. When a branch misprediction occurs, all instructions in the mispredicted path are discarded or flushed. Providing this solution will ensure that the power consumption is not adversely affected. It will prevent system owners from losing revenue from potential attacks and can save money on security upgrades after being compromised.
Allowable Subject Matter
Claims 9 and 17 objected to as being dependent upon a rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and further overcoming any other pending rejections/objections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Li (US 20210081575 A1) discloses [0058] “example of a specific version of a delay-based mitigation scheme using a taint matrix is discussed below with reference to FIGS. 7-10. In particular, this particular delay-based mitigation scheme uses a speculation shadow register and taint matrix in order to delay some but not all memory operations to address speculative side channel attacks.”
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/BASSAM A NOAMAN/Primary Examiner, Art Unit 2497
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