DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “One or more components configured to:” perform various functions such as retrieving, detecting and correcting in claim 1; “A memory controller configured to…” perform various functions such as retrieving, detecting and correcting in claim 17.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 11, 16, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schaefer, Scott (PG Pub. 2023/0,063,494 A1) [hereafter Schaefer].
As per claim 1, Schaefer teaches:
A memory device, comprising: one or more components configured to: retrieve, via one or more data pins associated with a user data block, host data; (Schaefer, ¶ [0040], write command issued by the host device; a data signal received on the DQ pins at the memory device and the memory device use the RDQS signal for sampling a received data signal, ¶ [0078], memory device receive data transmitted from host device for a write command)
retrieve, via one or more data mask inversion (DMI) pins associated with the user data block, error correction data; (Schaefer, ¶ [0040], DMI pin used to output error management information, ¶ [0101], ECC include information from DMI pin)
detect, using the host data and the error correction data, one or more multi-bit errors in the host data; and (Schaefer, ¶ [0048], correct one or more errors in the received data; correct and use received data having multiple bit errors, ¶ [0112], determining multiple bits error)
correct, using the host data and the error correction data, the one or more multi-bit errors (Schaefer, ¶ [0048], a host device attempting to correct and use received data having multiple bit errors; the host device may compare the received syndrome bits with the syndrome bits computed for the received data to detect (and, in some examples, correct) errors in the received data)
As per claim 10, the rejection of claim 1 is incorporated and Schaefer further teaches:
wherein the one or more components, to detect the one or more multi-bit errors in the host data, are configured to: compute, using the host data and the error correction data, a syndrome; and determine, using the syndrome, a pattern associated with the one or more multi-bit errors (Schaefer, ¶ [0048], syndrome bits to detect and/or correct one or more errors in the received data; error management information provided by the syndrome check signal, in combination with the error management information determined using the link ECC, may be used to decrease the likelihood of a host device attempting to correct and use received data having multiple bit errors, ¶ [0052])
Claims 11, 16 are method claims corresponding to the memory device claims 1, 10 respectively and are rejected for the same reasons set forth in connection of the rejections of claims 1, 10 above.
Claim 17 is a memory system claim corresponding to the memory device claim 1 and is rejected for the same reasons set forth in connection of the rejection of claim 1 above, and Schaefer further teaches:
A memory system, comprising: a media subsystem organized into multiple user data blocks; and (Schaefer, Fig. 1, ¶ [0028])
a memory controller in communication with the media subsystem via multiple channels, wherein each of the multiple channels corresponds to a respective user data block, of the multiple user data blocks, and wherein the memory controller is configured to, for each user data block, of the multiple user data blocks: (Schaefer, Fig. 1, ¶ [0041])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, and further in view of Brewer et al. (PG Pub. 2022/0,382,631 A1) [hereafter Brewer].
As per claim 2, the rejection of claim 1 is incorporated:
Schaefer does not teach:
wherein a host data portion of the user data block that is used to store the host data includes 64 bytes of storage, and wherein an error correction portion of the user data block that is used to store the error correction data includes 4 bytes of storage
However, Brewer in analogous art teaches:
wherein a host data portion of the user data block that is used to store the host data includes 64 bytes of storage, and wherein an error correction portion of the user data block that is used to store the error correction data includes 4 bytes of storage (Brewer, ¶ [0041], a first portion storing 64B user data, and a second portion storing 4B ECC data)
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Brewer into the method of Schaefer to provide a method wherein a host data portion of the user data block that is used to store the host data includes 64 bytes of storage, and wherein an error correction portion of the user data block that is used to store the error correction data includes 4 bytes of storage. The modification would be obvious because having different amount of data assigned for different types of data allows accessing the particular data types via different burst lengths (Brewer, ¶ [0041]).
As per claim 9, the rejection of claim 1 is incorporated:
Schaefer does not teach:
wherein the error correction data is associated with a Bose-Chaudhuri-Hocquenghem code capable of correcting at least a two-bit error
However, Brewer in analogous art teaches:
Bose-Chaudhuri-Hochquenghem (BCH) codes correcting multiple errors (Brewer, ¶ [0033], Bose-Chaudhuri-Hochquenghem (BCH) codes, ¶ [0049], correcting multiple errors, ¶ [0058], an error correction capability of correcting a quantity of errors not exceeding the threshold quantity)
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Brewer into the method of Schaefer to provide a method wherein a host data portion of the user data block that is used to store the host data includes 64 bytes of storage, and wherein an error correction portion of the user data block that is used to store the error correction data includes 4 bytes of storage. The modification would be obvious because it is possible to design binary BCH codes that can correct multiple bit errors.
Claim 18 is a memory system claim corresponding to the memory device claim 2 and is rejected for the same reasons set forth in connection of the rejection of claim 2 above.
Claim(s) 4, 5, 12, 13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, and further in view of Hampel et al. (WO 2022/119,704 A2) [hereafter Hampel].
As per claim 4, the rejection of claim 1 is incorporated:
Schaefer does not teach:
wherein the host data is associated with multiple data symbols, and wherein the error correction data is associated with a single symbol correction (SSC) code
However, Hampel in analogous art teaches:
error control scheme that provides single symbol correct (Hampel, ¶ [0010])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Hamel into the method of Schaefer to provide a method wherein the host data is associated with multiple data symbols, and wherein the error correction data is associated with a single symbol correction (SSC) code. The modification would be obvious because such error correction scheme provide single error correct double error detect protection/resiliency policy from one memory region and also access another region of the same memory device(s) using a more sophisticated non-binary block code that provides single symbol correct double symbol detect for 4-bit symbols (Hampel, ¶ [0010]).
As per claim 5, the rejection of claim 4 is incorporated and Hampel further teaches:
wherein the SSC code is one of a Reed-Solomon code or a non-binary Hamming code (Hampel, ¶ [0010], Reed-Solomon, Hamming code, non-binary block code)
Claims 12, 13 are method claims corresponding to the memory device claims 4, 5 respectively and are rejected for the same reasons set forth in connection of the rejections of claims 4, 5 above.
Claim 20 is a memory system claim corresponding to the memory device claim 4 and is rejected for the same reasons set forth in connection of the rejection of claim 4 above.
Claim(s) 7, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, Hampel, and further in view of Meaney et al. (PG Pub. 2019/0,163,565 A1) [hereafter Meaney].
As per claim 7, the rejection of claim 4 is incorporated:
Schaefer and Hampel do not teach:
wherein the error correction data is further associated with a cyclic redundancy check
However, Meaney in analogous art teaches:
host using Reed-Solomon ECC to provide the RAIM functionalities and at least one of the RAIM functionalities is selected from the group consisting of CRC checking (Meaney, ¶ [0083])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Meaney into the combined method of Schaefer and Meaney to provide a method wherein the error correction data is further associated with a cyclic redundancy check. The modification would be obvious because such ECC word identifies and corrects memory failures (Meaney, ¶ [0023]).
Claim 14 is a method claim corresponding to the memory device claim 7 and is rejected for the same reasons set forth in connection of the rejection of claim 7 above.
Claim(s) 8, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, and further in view of Song et al. (PG Pub. 2023/0,055,293 A1) [hereafter Song].
As per claim 8, the rejection of claim 1 is incorporated:
Schaefer does not teach:
wherein the one or more components are further configured to retrieve, via the one or more DMI pins, metadata associated with the user data block
However, Song in analogous art teaches:
receiving metadata over DMI pins (Song, ¶ [0045])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Song into the method of Schaefer to provide a method wherein the one or more components are further configured to retrieve, via the one or more DMI pins, metadata associated with the user data block. The modification would be obvious because data bus interface may be configured to transmit and receive data over the data bus and control information or metadata over the DMI pins (Song, ¶ [0045]).
Claim 15 is a memory method claim corresponding to the memory device claim 8 and is rejected for the same reasons set forth in connection of the rejection of claim 8 above.
Allowable Subject Matter
Claims 3, 6, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PG Pub. 2020/0,012,558 A1 discloses method of parity training for a dynamic random access memory by enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function.
PG Pub. 2019/0,340,067 A1 discloses a memory device comprising an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected.
PG Pub. 2021/0,124,699 A1 discloses a memory device including a data mask inversion (DMI) pin that provide parity data during a read operation.
PG Pub. 2022/0,180,958 A1 discloses a memory device comprising an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data.
See PTO-892 for other cited references not listed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAE M KO whose telephone number is (571)270-3886. The examiner can normally be reached M-F 9 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHAE M KO/Primary Examiner, Art Unit 2114