DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1-19 are indefinite because of the limitations “hard disk control system” and “hard disk control method”. The term “hard disk” is generally accepted in the art as referring to a memory architecture including magnetic spinning platters, which is contrary to the flash memory of the claimed invention. Consistent with the well-established axiom in patent law that a patentee or applicant is free to be his or her own lexicographer, a patentee or applicant may use terms in a manner contrary to or inconsistent with one or more of their ordinary meanings if the written description clearly redefines the terms. See, e.g., Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The Applicant’s Specification also describes the control system and control method in terms of flash, SSD NAND, and NAND flash. The use of the term “hard disk” when referring to a solid-state memory embodiment is contrary to or inconsistent with the ordinary meaning and the written description does not clearly redefine the claim term "so as to put a reasonable competitor or one reasonably skilled in the art on notice that the patentee intended to so redefine that claim term."
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, 11-12, 14-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagadomi et al. (US Pub. No. 2020/0065000), hereinafter referred to as Nagadomi.
Referring to claim 1, Nagadomi discloses a hard disk control system (fig. 4), comprising: a control module (fig. 4, NAND Controller 112), configured to receive operation information (processor 104 issues an access command, [0062]), and generate an operation signal and a chip selection signal according to the operation information (the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]); and at least one gating module (bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]), wherein each gating module comprises a plurality of output ports (NAND I/F 116 includes…IO signal pin 202…8-bit data elements IO0 to IO7 are input and output from the IO pin 202, [0050]), the plurality of output ports are connected with a plurality of flash loads (NAND memory 10 includes 4-channel NAND memory packages 10a to 10d…8 Stack Chip 10a1, [0031]) in a one-to-one correspondence manner (connecting the selected Chip, [0068]), and each gating module is configured to determine a target output port from the plurality of output ports according to the chip selection signal (the Chip Enable (CE) signals 0 to 3…connecting the selected Chip, [0068]), and transmit the operation signal to the corresponding flash load via the target output port, so that the flash load responds to the operation signal based on the chip selection signal (read/write with respect to the 8 Stack Chip 10a1, the 8 Stack Chip 10a2 is in a disconnected state, and in the case of read/write with respect to the 8 Stack Chip 10a2, 8 Stack Chip 10a1 is in the disconnected state, [0064]; the Chip Enable (CE) signals 0 to 3…connecting the selected Chip, [0068]).
As to claim 2, Nagadomi discloses each flash load comprises a plurality of execution units (NAND memory 10 includes 4-channel NAND memory packages 10a to 10d…8 Stack Chip 10a1, [0031]); and each flash load is configured to select any execution unit according to the chip selection signal to serve as an execution unit for responding to the operation signal (read/write with respect to the 8 Stack Chip 10a1, the 8 Stack Chip 10a2 is in a disconnected state, and in the case of read/write with respect to the 8 Stack Chip 10a2, 8 Stack Chip 10a1 is in the disconnected state, [0064]; the Chip Enable (CE) signals 0 to 3…connecting the selected Chip, [0068]).
As to claim 3, Nagadomi discloses each flash load and the control module are further configured to: send a channel connection of the chip selection signal (The NAND I/F 116 includes Ch0 controller 210a to Ch3 controller 210d, which are 4-channel interface circuits…Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]); receive the chip selection signal output by the control module via a channel, so as to select any execution unit according to the chip selection signal to serve as the execution unit for responding to the operation signal, wherein the chip selection signal is valid at a target level (Chip Enable (CE) signals 0 to 3 are input to the bus switches…bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]).
As to claim 4, Nagadomi discloses each flash load comprises a plurality of execution units (NAND memory 10 includes 4-channel NAND memory packages 10a to 10d…8 Stack Chip 10a1, [0031]), and the gating module is configured to: acquire the chip selection signal corresponding to each execution unit (Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]); determine an input gating signal based on all chip selection signals (Chip Enable (CE) signals 0 to 3 are input to the bus switches…bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, [0068]); and determine the target output port from the plurality of output ports according to the input gating signal (bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]), and the transmit the operation signal to the corresponding flash load via the target output port (Ch0 controller 210a includes…an FF_DATA [7:0] that latches IO[7:0] and outputs it, [0055]).
As to claim 5, Nagadomi discloses the gating module is further configured to receive a preset correspondence between the chip selection signals and the output ports (Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]); and the process of determining the target output port from the plurality of output ports according to the input gating signal comprises: determining the target output port according to the input gating signal and the correspondence (Chip Enable (CE) signals 0 to 3 are input to the bus switches…bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]).
As to claim 6, Nagadomi discloses each flash load comprises a plurality of execution units (NAND memory 10 includes 4-channel NAND memory packages 10a to 10d…8 Stack Chip 10a1, [0031]), the gating module comprises a logical processing unit and a switch control unit (fig. 11, ASIC NAND controller 112, Bus Switch Controller 220), the switch control unit comprises a first port and a plurality of second ports, the first port of the switch control unit is configured to acquire the operation signal generated by the control module, and the second ports serve as the output ports of the gating module; and the logical processing unit is configured to acquire the chip selection signal corresponding to each execution unit, determine the input gating signal based on all chip selection signals, determine the target output port from the plurality of output ports according to the input gating signal, and control the target output port to communicate with the first port of the switch control unit, so as to transmit the operation signal acquired by the first port of the switch control unit to the flash load connected with the target output port (one bus switch is provided in each 8 Stack Chip, and Chip Enable (CE) signals 0 to 3 are input to the bus switches 301a1 and 301a2…bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]).
As to claim 7, Nagadomi discloses the hard disk control system further comprises: a first configuration module (fig. 11, Ch0 Controller 210a), connected with a first configuration end of the gating module, and configured to configure the chip selection signal received by the gating module as an input signal (Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]).
As to claim 9, Nagadomi discloses the hard disk control system further comprises: a second configuration module (fig. 11, Ch1 Controller 210b), connected with a second configuration end of the gating module, and configured to configure the functions of the gating module (Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]).
As to claim 11, Nagadomi discloses the hard disk control system further comprises: a third configuration module (fig. 11, Ch2 Controller 210c), connected with a third configuration end of the gating module, and configured to enable a transmission channel of the gating module (Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]).
As to claim 12, Nagadomi discloses the gating module is a high-speed bus switch (the bus switches 301a1 and 301a2 for the IO signals, [0068]).
As to claim 14, Nagadomi discloses the operation signal comprises a read operation signal or a write operation signal (read/write from/in the NAND memory, [0059])
As to claim 15, Nagadomi discloses the gating module comprises a plurality of first ports, each first port of the gating module is configured to receive at least one chip selection signal (one bus switch is provided in each 8 Stack Chip, and Chip Enable (CE) signals 0 to 3 are input to the bus switches 301a1 and 301a2, [0068]), and the gating module is configured to: determine whether there is a valid chip selection signal in the chip selection signals received by each first port (Chip enable (CE) 0 to 3 signals from the NAND I/F 116 select the NAND packages 10a to 10d (NAND Ch0 to Ch3), [0050]); in a case that there is the valid chip selection signal in the chip selection signals received by each first port, determine a valid input gating signal based on the valid chip selection signal (bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]); and determine the target output port from the plurality of output ports according to the valid input gating signal, and transmit the operation signal to the corresponding flash load via the target output port, so that the flash load responds to the operation signal based on the chip selection signal (read/write with respect to the 8 Stack Chip 10a1, the 8 Stack Chip 10a2 is in a disconnected state, and in the case of read/write with respect to the 8 Stack Chip 10a2, 8 Stack Chip 10a1 is in the disconnected state, [0064]; the Chip Enable (CE) signals 0 to 3…connecting the selected Chip, [0068]).
Referring to claim 16, Nagadomi discloses a storage system, comprising the hard disk control system according to claim 1 (fig. 1).
Referring to claim 18, Nagadomi discloses a hard disk control method, applied to the hard disk control system (fig. 4) according to claim 1, wherein the hard disk control method comprises: acquiring a chip selection signal and an operation signal generated (the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]) based on operation information (read/write with respect to the 8 Stack Chip, [0064]); determining a target output port from all output ports of a gating module according to the chip selection signal (bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, [0068]); and transmitting the operation signal to a corresponding flash load (NAND memory 10 includes 4-channel NAND memory packages 10a to 10d…8 Stack Chip 10a1, [0031]) via the target output port, so that the flash load responds to the operation signal based on the chip selection signal (read/write with respect to the 8 Stack Chip 10a1, the 8 Stack Chip 10a2 is in a disconnected state, and in the case of read/write with respect to the 8 Stack Chip 10a2, 8 Stack Chip 10a1 is in the disconnected state, [0064]; the Chip Enable (CE) signals 0 to 3…connecting the selected Chip, [0068]).
Referring to claim 19, Nagadomi discloses an electronic device, comprising: a memory, configured to store a computer program; and a processor, configured to execute the computer program to implement the steps of the hard disk control method according to claim 18 (A processor 104 that controls the entire drive control circuit 4…boot program for booting respective management programs (firmware (FW)), [0044]).
Referring to claim 20, Nagadomi discloses a non-transitory readable storage medium, wherein a computer program is stored on the non-transitory readable storage medium, and when executed by a processor, the computer program (A processor 104 that controls the entire drive control circuit 4…boot program for booting respective management programs (firmware (FW)), [0044]) implements the following operations: acquiring a chip selection signal and an operation signal generated (the Chip Enable (CE) signals 0 to 3, and select (decode) a Chip to be accessed based on the access address, thereby connecting the selected Chip, [0068]) based on operation information (read/write with respect to the 8 Stack Chip, [0064]); determining a target output port from all output ports of a gating module according to the chip selection signal (bus switches 301a1 and 301a2 select a Chip group based on the Chip Enable (CE) signals 0 to 3, [0068]); and transmitting the operation signal to a corresponding flash load (NAND memory 10 includes 4-channel NAND memory packages 10a to 10d…8 Stack Chip 10a1, [0031]) via the target output port, so that the flash load responds to the operation signal based on the chip selection signal (read/write with respect to the 8 Stack Chip 10a1, the 8 Stack Chip 10a2 is in a disconnected state, and in the case of read/write with respect to the 8 Stack Chip 10a2, 8 Stack Chip 10a1 is in the disconnected state, [0064]; the Chip Enable (CE) signals 0 to 3…connecting the selected Chip, [0068]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nagadomi in view of Guo et al. (US Pub. No. 2022/0148663), hereinafter referred to as Guo.
As to claim 8, while Nagadomi discloses the first configuration module comprises a first end connected with a power supply module (fig. 1, power circuit 5), and a second end connected with the first configuration end (fig. 1, drive control circuit 4 connected between power supply module 5 and NAND channel ends), Nagadomi is silent regarding the specific drive circuitry and therefore does not appear to explicitly disclose a first resistor.
However, Guo discloses a power control architecture with resistors (peak power management (PPM) system for a memory chip with multiple memory dies…the multiple PPM circuits includes a pull-up driver electrically connected to a power source and a pull-up resistor; a pull-down driver electrically connected to a pull-down resistor; and a PPM pin connected to the pull-up resistor and the pull-down resistor, [0005]).
Nagadomi and Guo are analogous art because they are from the same field of endeavor, NAND memory architecture and operation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nagadomi and Guo before him or her, to modify the storage system of Nagadomi to include the power supply architecture of Guo because the resistor configuration would facilitate flexible power consumption control.
The suggestion/motivation for doing so would have been to optimize the memory performance and power consumption.
Therefore, it would have been obvious to combine Nagadomi and Guo to obtain the invention as specified in the instant claim.
As to claim 10, while Nagadomi discloses the second configuration module (fig. 11, Ch1 Controller 210b) a first end connected with the power supply module (fig. 1, power circuit 5), a second end and a first end both connected with the second configuration end (fig. 1, NAND Ch0-3 ends), Nagadomi is silent regarding the specific drive circuitry and therefore does not appear to explicitly disclose a second resistor and a third resistor, a first end of the second resistor is connected with the power supply module, a second end of the second resistor and a first end of the third resistor are both connected with the second configuration end, and a second end of the third resistor is grounded.
However, Guo discloses a second resistor and a third resistor, a first end of the second resistor is connected with the power supply module (peak power management (PPM) system for a memory chip with multiple memory dies…the multiple PPM circuits includes a pull-up driver electrically connected to a power source and a pull-up resistor; a pull-down driver electrically connected to a pull-down resistor; and a PPM pin connected to the pull-up resistor and the pull-down resistor, [0005]), a second end of the second resistor and a first end of the third resistor are both connected with the second configuration end, and a second end of the third resistor is grounded (PPM circuit 300 also includes a pull-down driver 336. In some embodiments, the pull-down driver 336 can be a MOSFET. In some embodiments, the pull-down driver 336 can be an n-channel MOSFET (i.e., nFET). A source terminal of the nFET 336 can be grounded, [0050]).
Nagadomi and Guo are analogous art because they are from the same field of endeavor, NAND memory architecture and operation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nagadomi and Guo before him or her, to modify the storage system of Nagadomi to include the power supply architecture of Guo because the resistor configuration would facilitate flexible power consumption control.
The suggestion/motivation for doing so would have been to optimize the memory performance and power consumption.
Therefore, it would have been obvious to combine Nagadomi and Guo to obtain the invention as specified in the instant claim.
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nagadomi in view of Ahwal et al. (US Pub. No. 2014/0047159), hereinafter referred to as Ahwal.
As to claim 13, Nagadomi does not appear to explicitly disclose the control module comprises a PCIe 3.0 controller.
However, Ahwal teaches the control module comprises a PCIe 3.0 controller (a Peripheral Component Interconnect Express ("PCIe") hub 214 that communicates with the FSMs 106…utilize PCIe 3.0, [0018]).
Nagadomi and Ahwal are analogous art because they are from the same field of endeavor, flash memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nagadomi and Ahwal before him or her, to substitute the anticipated communication standard of the storage system of Nagadomi with the PCIe 3.0 taught by Ahwal because Nagadomi demonstrates that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of an anticipated communication standard with the specific standard PCIe 3.0; Ahwal demonstrates that the substituted PCIe 3.0 standard was known in the art; and one of ordinary skill in the art could have substituted one known communication standard for another used for memory access, and the results of the substitution would have been a predictable storage interconnect.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Therefore, it would have been obvious to combine Nagadomi and Ahwal to obtain the invention as specified in the instant claim.
Referring to claim 17, while Nagadomi discloses the hard disk control system according to claim 1, Nagadomi does not appear to explicity disclose a server system embodiment.
However, Ahwal disclose a server embodiment of a storage system (flash memory devices in an enterprise server system, [0001]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Nagadomi and Ahwal before him or her, to implement of the storage system of Nagadomi as a server embodiment as taught by Ahwal because Nagadomi demonstrates a similar or analogous flash memory system to the claimed variation and Ahwal demonstrates the use of flash memory in a predictable server embodiment, and known work in one field of endeavor may prompt variations of It for use in either the same field or a different one.
The rationale to support a conclusion that the claimed invention would have been obvious is that design incentives or other market forces could have prompted one of ordinary skill in the art to vary the prior art in a predictable manner to result in the claimed invention. (MPEP 2143.I.F).
Therefore, it would have been obvious to combine Nagadomi and Ahwal to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2022/0391087 of Tang et al., the US Pub. No. 2020/0167298 of Yang et al., and the US Pub. No. 2014/0293705 of Gillingham et al. are pertinent to flash memory systems including chip select control.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center. For more information about the Patent Center, see https://patentcenter.uspto.gov/. Should you have questions on access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
Prosecution Insights