Prosecution Insights
Last updated: October 23, 2026
Application No. 19/051,580

POWER LOSS PROTECTION CIRCUIT, DATA STORAGE MODULE, AND SERVER

Non-Final OA §103
Filed
Feb 12, 2025
Priority
Feb 15, 2024 — JP 2024-021511
Examiner
CHOI, SEUNG HO
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
22 granted / 22 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
16 currently pending
Career history
47
Total Applications
across all art units

Statute-Specific Performance

§101
3.2%
-36.8% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
36.5%
-3.5% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 22 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the application filed on 12 February 2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, and 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gregory C. White (US 3573483 A; hereafter “White”) in view of Akira Uryu et. al (US 2020/0409442 Al; hereafter “Akira”). -Regarding claim 1: White discloses: PNG media_image1.png 582 1170 media_image1.png Greyscale A power loss protection circuit comprising: a first input terminal (Fig. 1; 12) configured to receive, as an input voltage, a voltage generated by an intermediate bus converter configured to step down a DC bus voltage (Fig. 1; 10, and description of the preferred embodiment; “Rectifier 8 converts the alternating current received from source 6 to direct current”) a second input terminal (Fig. 1; 20) configured to receive the DC bus voltage (description of the preferred embodiment; “Rectifier 8 converts the alternating current received from source 6 to direct current”); a capacitor connection terminal (Fig. 1; 22) to which an is to be connected; an output terminal to which a load is to be connected (Fig. 1; 14 to LOAD 16); a first switch connected between the first input terminal and the output terminal (Fig. 1; 46 as a switch) ; a charging circuit connected between the second input terminal and the capacitor connection terminal (Fig. 1; 18 connected between 20 and 22); and an internal converter (Fig. 1; isolating device 30) configured to step down a voltage of the capacitor connection terminal (I would say that it must have some level of resistance so when it conducts current there will be a voltage drop.) and stabilize an output voltage (summary of the invention; ” the isolating device is biased into the conducting state in response to the switching of the variable resistance device, allowing current to flow from the battery to the load, thereby maintaining a proper voltage across the load.”). However, White does not disclose an external capacitor in power loss protection circuit. Akira, in the same field of endeavor, discloses: which an external capacitor (Fig. 1; 34) is to be connected….. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in White such that a commonly used external capacitor described in Akira is applied to the power loss protection circuit. Doing so allows to implement a back-up circuit in the power loss protection circuit. -Regarding claim 13: White discloses: a first terminal (Fig. 1; 12) configured to receive a first voltage, which is an output voltage of an intermediate bus converter (Fig. 1; 10), from the server; a second terminal (Fig. 1; 20) configured to receive a second voltage, which is an input voltage of the intermediate bus converter (Fig. 1; 10, and description of the preferred embodiment; “Rectifier 8 converts the alternating current received from source 6 to direct current”), from the server; a power supply circuit; and a power loss protection circuit configured to receive the first voltage and the second voltage and supply a power supply voltage to the power supply circuit, wherein the power loss protection circuit includes: ; a first switch connected between the first terminal and an input terminal of the power supply circuit (Fig. 1; 46 as a switch); a charging circuit connected between the second terminal and the capacitor (Fig. 1; 18 connected between 20 and 22, where battery could be replaced by a capacitor through Akira); and an internal converter (Fig. 1; isolating device 30) configured to step down a voltage of the capacitor (I would say that it must have some level of resistance so when it conducts current there will be a voltage drop.) and supply an output voltage stabilized at a target level (summary of the invention; ” the isolating device is biased into the conducting state in response to the switching of the variable resistance device, allowing current to flow from the battery to the load, thereby maintaining a proper voltage across the load.”) to the power supply circuit. Akira, in the same field of endeavor, discloses: A data storage module that is a solid state disk (SSD) module (paragraph 0099; “The data storage apparatus 300 is configured as an SSD (Solid State Drive), for example.”)…………. ……..a capacitor (Fig. 1; 34)….. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in White such that a commonly used external capacitor and SSD module described in Akira is applied to the power loss protection circuit. Doing so allows to implement a back-up circuit in the power loss protection circuit. -Regarding claim 2: Akira discloses: The power loss protection circuit of Claim 1, wherein the target level of the internal converter is lower than the input voltage (Fig. 2; 110, step down converter), and the internal converter operates regardless of presence or absence of the input voltage (paragraph 0035; “When the step-down converter 110 is set to the enabled state by the controller 130”). -Regarding claim 3: Akira discloses: The power loss protection circuit of Claim 1, wherein the internal converter is enabled when the input voltage is interrupted (paragraph 0035; “When the step-down converter 110 is set to the enabled state by the controller 130”). -Regarding claim 4: Akira discloses: The power loss protection circuit of Claim 1, wherein the charging circuit includes a second switch (Fig. 4; step-up converter includes SW3, and paragraph 0006; “During a period in which the input voltage VIN is supplied, the step-up converter 36 steps up the input voltage VIN' and charges the backup capacitor 34.”), and an on-resistance of the second switch is higher than an on-resistance of the first switch (in detailed description, target voltage is larger than supply voltage, which is related to on-resistance). -Regarding claim 9: Akira discloses: The power loss protection circuit of Claim 1, wherein the charging circuit operates so that the voltage of the capacitor connection terminal does not exceed a predetermined voltage of 35 V or lower (paragraph 0054; “such that the capacitor voltage Vstorage approaches a target level (30 V).”). -Regarding claim 10: Akira discloses: The power loss protection circuit of Claim 9, wherein the charging circuit includes: a second switch; and a control circuit configured to turn off the second switch when the voltage of the capacitor connection terminal exceeds the predetermined voltage (paragraph 0054; “after the capacitor voltage Vstorage reaches the target level, the switching controller 212 may turn off the switch SW3,”). -Regarding claim 11: Akira discloses: The power loss protection circuit of Claim 9, wherein the charging circuit includes a regulator (Fig. 4; 214, converter controller) configured to stabilize the voltage of the capacitor connection terminal (paragraph 0046; “step-up converter 36 is capable of maintaining the output of the voltage level 12 V required by the load”). -Regarding claim 12: Akira discloses: The power loss protection circuit of Claim 1, wherein the charging circuit (Fig. 4; step-up converter 120) further includes a clamp circuit (Fig. 4; SW3) configured to clamp the voltage of the capacitor connection terminal so as not to exceed a predetermined voltage (paragraph 0054; “after the capacitor voltage Vstorage reaches the target level, the switching controller 212 may turn off the switch SW3,”). -Regarding claim 14: Akira discloses: The data storage module of Claim 13, wherein the internal converter is turned on regardless of presence or absence of the first voltage (paragraph 0035; “When the step-down converter 110 is set to the enabled state by the controller 130”), and the target level of the internal converter is lower than the first voltage (Fig. 2; 110, step down converter). -Regarding claim 15: Akira discloses: The data storage module of Claim 13, wherein the internal converter is turned on when the first voltage is interrupted (paragraph 0035; “When the step-down converter 110 is set to the enabled state by the controller 130”). -Regarding claim 16: Akira discloses: The data storage module of Claim 13, wherein the charging circuit includes a second switch (Fig. 4; step-up converter includes SW3, and paragraph 0006; “During a period in which the input voltage VIN is supplied, the step-up converter 36 steps up the input voltage VIN' and charges the backup capacitor 34.”), and an on-resistance of the second switch is higher than an on-resistance of the first switch (in detailed description, target voltage is larger than supply voltage, which is related to on-resistance). Allowable Subject Matter Claims 5-8, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. The following is a statement of reasons for the indication of allowable subject matter: -with respect to claim 5: the prior arts in White, and Akira disclose the claimed invention in basic claims but do not further disclose about a third switch connected between an output of the internal converter and the output terminal. -with respect to claim 17: the prior arts in White, and Akira disclose the claimed invention in basic claims but do not further disclose about a third switch connected between an output of the internal converter and the input terminal of the power supply circuit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEUNG HO CHOI/Examiner, Art Unit 2838 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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Prosecution Timeline

Feb 12, 2025
Application Filed
Oct 15, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 1m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 22 resolved cases by this examiner. Grant probability derived from career allowance rate.

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