DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Request for Reconsideration
This final Office action is in response to the Request for Reconsideration filed 7/1/26. No claims were amended or canceled, so claims 1-33 remain pending. Applicant’s arguments are not persuasive, so the rejections are repeated and made final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-13, 15-22, 24-29, and 31-33 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2016/0350015 to LUO et al. in view of U.S. Patent Application Publication 2022/0405090 to VELUSWAMY et al.
Regarding claims 1, 10, and 19, LUO shows the claimed processing circuitry in Fig. 1 as processor(s) 116. He shows the claimed random access memory as DRAM 110. He shows the NAND memory as flash 112.
LUO mentions writing data from the flash to the DRAM at 0032 (“The data can be restored from the flash during recovery.”, 0047 (“qNVRAM can also have save and restore routines that flush/load data to/from the underlying flash storage 108,” emphasis added), and 0051 (“The qNVRAM system 100 also has save and restore routines that can flush/load data to/from the underlying flash storage 112,” emphasis added). LUO does not teach that this data is control information, but neither does his mention of “data” exclude control information.
VELUSWAMY also discloses a system that flushes data to a nonvolatile memory in the event of a reset (see 0080-0081). He explicitly teaches that the data flushed to (and by implication, read from) the nonvolatile memory is a type of control information called a virtual-to-physical (V2P) mapping table.
It would have been obvious to one skilled in the art at the time of the effective filing date to flush control information in LUO’s device since control information (such as mapping tables) is important to save in the event of a loss of power to a volatile memory, such as a DRAM.
LUO mentions the claimed hard reset and flush operations at 0030, 0032, 0044, 0047, 0051, 0086, Table 3, and elsewhere.
Regarding claims 2, 8, 11, 17, 20, 26, and 32, the combination of LUO and VELUSWAMY flushes data associated with a host and control information as discussed above. Neither LUO nor VELUSWAMY specifically teaches flushing control information after flushing data associated with a host, however the decision of whether to flush the control information before or after flushing the data associated with a host is an obvious matter of design choice. They should both be flushed, and they cannot be flushed at the same time, so one has to be flushed before the other.
Regarding claims 3, 12, 21, and 28, LUO’s device performs a hard reset which performs a memory reset operation as claimed. VELUSWAMY’s device similarly performs a memory reset operation.
Regarding claims 4, 13, 22, and 29, LUO does not mention the claimed idle/active state determination, however it would have been obvious to one skilled in the art at the time of the effective filing date to determine whether the memory system is in an active state prior to flushing because memory that is in an active state might lose the data it is processing if a read/write isn’t complete before the flushing begins.
Regarding claims 6, 15, 24, and 31, LUO does not mention determining whether writes have occurred since a previous reset or initialization operation, however his flushing operation certainly only flushes dirty (stale) data so his device inherently considers the presence of writes that have occurred since a previous reset. In other words, if no writes have occurred since a previous reset, then there will be no dirty data to flush, so no flushing will be necessary. If writes have occurred since a previous reset, there will be dirty data to flush upon the next reset, so in the system’s determination of what data to flush, it inherently determines whether any dirty data exists and therefore whether a flush is necessary.
Regarding claims 7, 16, and 25, VELUSWAMY mentions a virtual-to-physical (V2P) mapping table which is analogous to the claimed logical-to-physical (L2P) mapping information.
Regarding claims 9, 18, 27, and 33, it can be said that all operations performed by the processing circuitry are based at least in part on a bootup operation sequence since the bootup operation sequence is what prepares the processing circuitry to operate.
Allowable Subject Matter
Claims 5, 14, 23, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 7/1/26 have been fully considered but they are not persuasive.
Applicant has essentially only one argument, presented at the top of page 12 (“VELUSWAMY teaches avoiding flushing a V2P mapping table during a reset operation”); again in the first full paragraph of page 12 (“VELUSWAMY describes a process in which the V2P mapping table is skipped over during flushing to reduce latency”); and again in the last paragraph of page 12 (“VELUSWAMY would lead the skilled person in the opposite direction---toward skipping such a flush to reduce latency”).
First of all, the Examiner was relying on VELUSWAMY solely for the teaching of the type of control information that is flushed to and restored from nonvolatile memory. VELUSWAMY clearly teaches that it was known to flush V2P mapping table control information to nonvolatile memory.
Secondly, Applicant’s argument that VELUSWAMY teaches skipping the flush of V2P information to reduce latency is an oversimplification of VELUSWAMY’s disclosure. It is true that VELUSWAMY teaches forgoing flushing V2P information in one instance (namely just prior to downloading a firmware update as taught at 0035-0038 and 0058-0060), but it is also true that VELUSWAMY clearly teaches the conventional reset processing step of flushing V2P data to nonvolatile memory when the forgo flushing flag is not set (see 0071 and 0081, step 320 in Fig. 3, and step 410 in Fig. 4 for example).
So while it is true that VELUSWAMY teaches skipping the flushing step in one instance (such as when the firmware is being updated), it is also true that VELUSWAMY teaches not skipping the flushing step in other instances (such as upon an unexpected power loss, as mentioned by LUO, when it’s important to preserve “dirty” data that hasn’t been copied back to nonvolatile memory yet).
The clear teaching of VELUSWAMY is that
“The data storage device 120 may map the LBA to a PBA that changes during operation of the data storage device 120. The data storage device 120 may non-volatilely store a copy (e.g., a V2P mapping table 129B) in the NVM devices 140 for purposes of retention between power cycles. To enable more efficient access (in terms of access times), the data storage device 120 may, however, load or retain a copy (e.g., the V2P mapping table 129A) in the volatile memory 127.” (paragraph 0031)
When data is copied from nonvolatile memory to volatile memory for efficiency, and then modified in volatile memory, it must be flushed back to nonvolatile memory eventually (such as when power is lost) so that the modified data is not lost. This is the conventional situation of flushing the V2P information back to nonvolatile memory mentioned by VELUSWAMY. The non-conventional operation mentioned by VELUSWAMY of forgoing the flushing of V2P information is for the special situation when a firmware update is about to be downloaded.
So not only does VELUSWAMY teach that one type of control information is V2P mapping table information, he also clearly teaches that the conventional operation is to flush V2P data to nonvolatile memory upon a system reset (see 0034, 0070-0071, and 0080-0081).
In light of these two facts, Applicant’s arguments are not persuasive.
Note
It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132
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