DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 6/22/26 is acknowledged. The traversal is on the ground(s) that the Restriction Requirement does not identify any structural feature that distinguishes the asserted species, that there is no serious search burden, and that they are not mutually exclusive. This is not found persuasive because for example, fig. 5a shows parallel paths while fig. 6a shows a single path with protection circuits 72 and 74, and 70 between 40 and 10. There is a search burden since they would require different search strategies. They are mutually exclusive because fig. 5a shows the parallel path and lack of 70, 72, 74 while fig. 6a shows a single path with 70, 72, 74, among other differences.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 12 and 15, it claims that the first FET 10 is in parallel with a third FET 50. While Examiner agrees with the specification where it describes that 10 and 40 together are in parallel with 50 and 60 together. It is unclear how 10 and 50 are in parallel separately since their sources are not coupled. A similar issues arises for claim 15 with the claimed parallel fourth FET 160 with the second FET 40/140. It is unclear how 140 and 160 are in parallel separately since their sources are not coupled.
Regarding claims 13 and 18, reference is made to "a voltage reference." However, such a voltage reference was introduced in parent claim 2. In claim 2, it appears that the fifth FET is 122 so the voltage reference is VDD. In claim 13, it appears that the seventh FET is 172, making the voltage reference VSS. The same applies in claim 18. It is unclear if these should be renamed to reflect that they coupled to different voltages.
Regarding claims 14, 16, and 17, these claims are rejected since it depends on claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hunter (US 2019/0393707) in view of Stultz (US 2014/0132311) in view of Cho (US 2021/0099656).
Regarding claim 1, fig. 1 of Hunter discloses a solid state switch, comprising: a first field-effect transistor [106], FET, comprising: a first terminal, a second terminal, a bulk terminal and a gate terminal, and configured to be switched between an on-state and an off-state; a second FET [108] in series with the first FET, wherein the second FET comprises a first terminal, a second terminal, a bulk terminal, and a gate terminal, and wherein the second terminal of the first FET is connected to the second terminal of the second FET. Hunter does not disclose a first device coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET. However, fig. 1 of Stultz discloses a bulk driver 103 coupled between a terminal of the switch 101 and the bulk of the switch. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the bulk driver at the bulks of 106 and 108 as taught in Stultz for the purpose of utilizing a suitable and well-known type of bulk control for a transistor for improved control and performance. Hunter in view of Stultz discloses the combination as indicated above except for where the bulk driver is a buffer. However, Cho describes implementing a driver with a buffer (par. 69). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the buffer as taught in Cho for the purpose of utilizing a suitable and well-known type of driver implementation.
Regarding claim 4, the combination as indicated above discloses a second buffer [the buffer at the bulk of 108 after the combination described above] comprising an output terminal coupled to the bulk terminal of the second FET, and an input terminal coupled to the first terminal of the second FET.
Regarding claim 8, the combination as indicated above discloses wherein the first and second FET are both a first-type FET, wherein the first-type is n-type or p-type.
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hunter in view of Stultz in view of Cho, further in view of Tsao.
Regarding claim 7, the combination as indicated above teaches the device of claim 1 as described. The combination does not teach wherein the first buffer is a UGB so as to reduce leakage at the first terminal of the first FET. However, Tsao describes implementing a buffer as a unity gain buffer (par. 36). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the unity gain buffer as taught in Tsao for the purpose of utilizing a suitable and well-known type of buffer design.
Regarding claim 19, the combination as indicated above teaches the device of claim 1 as described. The combination does not teach wherein the first buffer is: a unity gain buffer, UGB; a voltage follower; or a cascade complementary source follower. However, Tsao describes implementing a buffer as a unity gain buffer (par. 36). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the unity gain buffer as taught in Tsao for the purpose of utilizing a suitable and well-known type of buffer design.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hunter in view of Stultz.
Regarding claim 20, fig. 1 of Hunter discloses a solid state switch, comprising: a first field-effect transistor [106], FET, comprising: a first terminal, a second terminal, a bulk terminal and a gate terminal, and configured to be switched between an on-state and an off-state; a second FET [108] in series with the first FET, wherein the second FET comprises a first terminal, a second terminal, a bulk terminal, and a gate terminal, and wherein the second terminal of the first FET is connected to the second terminal of the second FET. Hunter does not disclose means for providing current sources to the bulk terminals of the first and second FETs. However, fig. 1 of Stultz discloses a bulk driver 103 coupled between a terminal of the switch 101 and the bulk of the switch. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the bulk driver at the bulks of 106 and 108 as taught in Stultz for the purpose of utilizing a suitable and well-known type of bulk control for a transistor for improved control and performance.
Allowable Subject Matter
Claims 2, 3, 5, and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIBIN CHEN/Primary Examiner, Art Unit 2836
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