DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 07/15/2026. Claims 1, 12, and 21 have been amended. Claims 1-21 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed provisional application, 63/561,658, is acknowledged.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(2) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6, 10, 11, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US2024/0126663), hereinafter Cho in view of Hadar et al. (US 2022/0014400), hereinafter Hadar, and further in view of Tan et al. (WO 2022/226783), hereinafter Tan, Hansson et al. (US2018/0089079), hereinafter Hansson and Wei et al. (US2024/0144982), hereinafter Wei.
Regarding claims 1 and 21, taking claim 1 as exemplary, Cho teaches a memory system, comprising:
one or more memory devices (Cho, [0028], memory devices 13; Fig.1); and
processing circuitry (Cho, [00028], controller 12; Fig.1) coupled with the one or more memory devices and configured to cause the memory system to:
establish, while the memory system operates according to a first power state, a communications link between the memory system and a host system, the communications link based at least in part on one or more first parameters associated with a first protocol layer (Cho, [0032], The controller 12 may include a PCIe controller (PCTR) 18 that establishes a link between an external host and a PCIe interface; [0033], the PCIe controller 18 may proceed with a link-up process of establishing a link between an external host and the storage device 10 by determining values of PHY parameters that may be configured in the physical layer; [0041], In order to exchange data with each other, when the power of the system 20 is turned on and the power is supplied to the host 30, the storage device 40, and the graphic processing device 50, the link-up process configuring the links between the interfaces 31A, 31B, 41, and 51 may be executed.);
determine whether a temperature metric of the memory system satisfies a threshold based on a power state of the memory system changing from the first power state to a second power state (Cho, [0042], when a device connected to the PCIe interface is changed or the external temperature and the power are changed, the performance of the system 20 may deteriorate; [0045], internal temperature of the storage device);
enable a resistor termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold; and
communicate, while operating according to the second power state and based at least in part on the temperature metric satisfying the threshold, data from the memory system using the communications link based at least in part on one or more second parameters associated with the first protocol layer and the resistor termination scheme, wherein the one or more second parameters are different from the one or more first parameters (Cho, [0042]; [0043], when … or the external temperature and the power are changed, by changing the PHY parameters as needed … the PCIe interface may be controlled in an optimal condition; [0077], In addition, as at least one of the PHY parameters is configured with a different value, at least one of the data signals DATA0 and DATA1 transmitted through the same lane have different waveforms).
Cho teaches changes in temperature and power, nevertheless, Cho does not explicitly teach determining a temperature metric satisfies a threshold based on changes in power state, as claimed. Cho also does not explicitly teach enable a resistor termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold, as claimed.
However, Cho in view of Hadar teaches temperature metric of memory system satisfying the threshold (Hadar, [0024], When the temperature is below a certain threshold, the VGA gain is set to a low value; [0030], if the current die temperature is in the mid-range, between a low threshold and a high threshold, the VGA gain initial target will be for a mid-gain value; [0020]; [0021], FIG. 2 shows receiver equalization components 200 implemented in a receiver PHY (Physical Layer) that are used to establish initial link equalization parameters and subsequently adjust the link signals to adapt to changes in the platform temperature).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cho to incorporate teachings of Hadar to determine changes in temperature by comparing the temperature with a threshold value. A person of ordinary skill in the art would have been motivated to combine the teachings of Cho with Hadar because it improves efficiency of the storage system disclosed in Cho by defining a clear limit in order to detect abnormal conditions quickly.
The combination of Cho does not explicitly teach a first power state is changed to a second power state and enable a resistor termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold, as claimed.
However, the combination of Cho in view of Tan teaches determine whether a temperature metric of the memory system satisfies a threshold based on a power state of the memory system changing from the first power state to a second power state (Tan, [0053], deactivated state … low-power state mode … hibernate state; [0062], At 425, a voltage transition occurs; [0064], At 430, a second temperature is determined; [0064], At 435, whether the second temperature exceeds a second temperature threshold is determined; Hadar, [0024], [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate changes of Tan to determine whether a temperature of a memory system satisfies a threshold after power state of the memory system changed from a first power state to a second power state. If the temperature of the memory system satisfies a threshold at a power state, PHY parameters can be adjusted. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Tan because it improves efficiency of the storage system disclosed in the combination of Cho by allowing dynamic thermal operations based on different power states.
The combination of Cho does not explicitly teach enable a resistor termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold, as claimed.
However, the combination of Cho in view of Hansson and Wei teaches enable a resistor termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold (Hansson, [0047], perform a termination setting operation to configure termination components within the associated memory module dependent on whether a currently processed command identifies the direct data transfer or identifies a transfer to be performed between the memory controller and the associated memory module; [0092], Over time, drift can be introduced into the signals propagating over the connection between the physical layer interface 35 and the portion of memory 40 due to a variety of factors, for example changes in operating temperature and voltage, etc. Hence, periodically a training operation may need to be performed on the physical layer interface 35 in order to update the configuration of the synchronisation control block 150; [0106]; [0121]; Fig.12; Wei, [0057], providing an ODT configuration value to an ODT configuration circuit. Generally, an ODT Rtt circuit block may provide one of several possible termination resistances (Rtt). The termination resistance provided by the ODT Rtt circuit block may be determined by enabling and disabling various pathways within the ODT Rtt circuit block, so as to “program” or “configure” the ODT Rtt circuit block to effectively provide the desired termination resistance);
communicate, while operating according to the second power state and based at least in part on the temperature metric satisfying the threshold, data from the memory system using the communications link based at least in part on one or more second parameters associated with the first protocol layer and the resistor termination scheme, wherein the one or more second parameters are different from the one or more first parameters (Hansson, [0043], The physical layer interface operates in a manner to maintain synchronised communication across that physical connection between the memory controller and the memory modules; [0045]; [0091]; [0118], the synchronisation control settings are updated within the synchronisation control block; Cho, [0042]; [0043]; [0077])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Hansson to initiate a training/calibration operation associated with termination resistor setting in response to determining that operating temperature exceeds a threshold. The updated termination resistor settings are communicated across physical connections. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Hansson because it improves efficiency and accuracy of the storage system disclosed in the combination of Cho by ensuring that synchronized communication is maintained across the various paths used during data transfer (Hansson, [0045]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Wei to enable/disable various pathways of a termination resistor circuit in order to provide a desired termination resistance/impedance. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Wei because it improves efficiency and accuracy of the storage system disclosed in the combination of Cho by providing a desired termination resistance/ impedance using various resister termination scheme.
Claim 21 has similar limitations as claim 1 and is rejected for the similar reasons.
Regarding claim 3, the combination of Cho teaches all the features with respect to claim 1 as outlined above. The combination of Cho further teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: update one or more parameters associated with the first protocol layer from the one or more first parameters to the one or more second parameters based at least in part on determining that the temperature metric satisfies the threshold (Hadar, [0021], FIG. 2 shows receiver equalization components 200 implemented in a receiver PHY (Physical Layer) that are used to establish initial link equalization parameters and subsequently adjust the link signals to adapt to changes in the platform temperature; [0024], When the temperature is below a certain threshold, the VGA gain is set to a low value; Cho, [0043] ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cho to incorporate teachings of Hadar to determine changes in temperature by comparing the temperature with a threshold value and update one or more PHY parameters when the temperature satisfies the threshold value. A person of ordinary skill in the art would have been motivated to combine the teachings of Cho with Hadar because it improves efficiency of the storage system disclosed in Cho by defining a clear limit in order to detect abnormal conditions quickly.
Regarding claim 6, the combination of Cho teaches all the features with respect to claim 1 as outlined above. The combination of Cho further teaches the memory system of claim 1, wherein determining whether the temperature metric satisfies the threshold comprises the processing circuitry configured to cause the memory system to: determine whether the temperature metric is above the threshold; determine whether the temperature metric meets the threshold; or determine whether the temperature metric is below the threshold (Cho, [0042]; Hadar, [0024], When the temperature is below a certain threshold; [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cho to incorporate teachings of Hadar to determine changes in temperature by comparing the temperature with a threshold value. A person of ordinary skill in the art would have been motivated to combine the teachings of Cho with Hadar because it improves efficiency of the storage system disclosed in Cho by defining a clear limit in order to detect abnormal conditions quickly.
Regarding claim 10, the combination of Cho teaches all the features with respect to claim 1 as outlined above. The combination of Cho further teaches the memory system of claim 1, wherein the first protocol layer comprises a physical layer (Cho, [0003], In order for the semiconductor devices to exchange the data with each other through the PCIe interface, a process of setting a link in a physical layer (PHY) of the PCIe interface; [0033], the PCIe controller 18 may proceed with a link-up process of establishing a link between an external host and the storage device 10 by determining values of PHY parameters that may be configured in the physical layer).
Regarding claim 11, the combination of Cho teaches all the features with respect to claim 1 as outlined above. The combination of Cho further teaches the memory system of claim l, wherein the processing circuitry is further configured to cause the memory system to: communicate, while operating according to the first power state and based at least in part on establishing the communications link, second data from the memory system using the communications link based at least in part on one or more first parameters associated with the first protocol layer (Cho, [0057]; [0061], at least one of the LTSSM 115 of the first semiconductor device 110 and the LTSSM 125 of the second semiconductor device 120 may performs a link-up process for configuring the link 130 for the first and second semiconductor devices 110 and 120 to send and receive data with each other; [0063], at least one of the LTSSM 115 of the first semiconductor device 110 and the LTSSM 125 of the second semiconductor device 120 may performs a link-up process for configuring the link 130 for the first and second semiconductor devices 110 and 120 to send and receive data with each other).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cho, Hadar, Tan, Hansson, and Wei as applied to claim 1 above, and further in view of Noh et al. (US2021/0216223), hereinafter Noh.
Regarding claim 2, the combination of Cho teaches all the features with respect to claim 1 as outlined above. The combination of Cho does not explicitly teach the memory system of claim 1, wherein the first power state comprises a disable state, a hibernate state, a sleep state, a stall state, or an unpowered state and the second power state is different from the first power state and comprises the disable state, the hibernate state, or the sleep state, as claimed.
However, the combination of Cho in view of Noh teaches the memory system of claim 1, wherein the first power state comprises a disable state, a hibernate state, a sleep state, a stall state, or an unpowered state and the second power state is different from the first power state and comprises the disable state, the hibernate state, or the sleep state (Noh, [0114]; [0116], upon switching from the hibernate state HIBERN8 to the sleep state SLEEP or the stall state STALL).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Noh to transition power between a hibernate state and a sleep state if needed. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Noh because it improves efficiency of the storage system disclosed in the combination of Cho by selecting a most energy efficient power state for a memory system.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cho, Hadar, Tan, Hansson, and Wei as applied to claim 3 above, and further in view of Kashem et al. (US12,265,467), hereinafter Kashem.
Regarding claim 4, the combination of Cho teaches all the features with respect to claim 3 as outlined above. The combination of Cho does not explicitly teach the memory system of claim 3, wherein updating the one or more parameters from the one or more first parameters to the one or more second parameters comprises the processing circuitry configured to cause the memory system to: adjust a resistor termination scheme associated with the first protocol layer, as claimed.
However, the combination of Cho in view of Kashem teaches the memory system of claim 3, wherein updating the one or more parameters from the one or more first parameters to the one or more second parameters comprises the processing circuitry configured to cause the memory system to: adjust a resistor termination scheme associated with the first protocol layer (Kashem, col.7, lines 1-17, Training is performed by the PHY 122 (e.g., at startup, adjustably during operation, etc.) to set parameters of the physical interface 124 in order to optimize communication. Examples of parameters set as part of training include impedance calibration which is set by adjusting termination resistance values in the PHY 122 and the physical memory 110).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Kashem to adjust termination resistance value as physical layer parameters in order to optimize communications between devices. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Kashem because it improves efficiency of the storage system disclosed in the combination of Cho by providing different termination resistance values for different link conditions such as high-speed operations and low-power operations.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cho, Hadar, Tan, Hansson, and Wei as applied to claim 3 above, and further in view of Kashem et al. (US12,265,467), hereinafter Kashem and Wang et al. (US2022/0283622), hereinafter Wang.
Regarding claim 5, the combination of Cho teaches all the features with respect to claim 3 as outlined above. The combination of Cho does not explicitly teach the memory system of claim 3, wherein updating the one or more parameters from the one or more first parameters to the one or more second parameters comprises the processing circuitry configured to cause the memory system to: adjust a range of values corresponding to a voltage controlled oscillator associated with the first protocol layer, as claimed.
However, the combination of Cho in view of Kashem teaches the memory system of claim 3, wherein updating the one or more parameters from the one or more first parameters to the one or more second parameters comprises the processing circuitry configured to cause the memory system to: adjust a range of values corresponding to a voltage controlled oscillator associated with the first protocol layer (Kashem, col.7, lines 1-17, Training is performed by the PHY 122 (e.g., at startup, adjustably during operation, etc.) to set parameters of the physical interface 124 in order to optimize communication … Voltage and timing reference parameters are also set as part of training by adjusting voltage levels and clock phase to establish a common voltage and timing reference for signals communicated between the PHY 122 and the physical memory 110.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Kashem to adjust voltage levels and clock phase to establish a common voltage and timing reference for signals communicated between the PHY 122 and the physical memory 110 . A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Kashem because it improves efficiency of the storage system disclosed in the combination of Cho by providing different termination resistance values for different link conditions such as high-speed operations and low-power operations.
The combination of Cho teaches PHY includes voltage and timing reference parameters which can be adjusted in order to establish a voltage and timing reference for communication signals, nevertheless, the combination of Cho does not explicitly teach that voltage and timing references are based on a voltage control oscillator, as claimed.
However, the combination of Cho in view of Wang teaches adjust a range of values corresponding to a voltage controlled oscillator associated with the first protocol layer (Wang, [0058], The vendor-specific M-PHY layer can implement a voltage-controlled oscillator (VCO)-based circuit to generate a clock signal corresponding to the data channel between the host 10 and the storage device 20, wherein the frequency of the clock signal is controlled by inputting voltage signals of different magnitudes to the voltage control oscillator; Kashem, col.7, lines 1-17).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Wang to implement a voltage-controlled oscillator to generate voltage and timing reference parameters used by PHY. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Wang because it improves efficiency of the storage system disclosed in the combination of Cho by dynamically adjusting timing parameters when temperature and/or voltage changes, which improves reliability of high-speed links.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cho, Hadar, Tan, Hansson, and Wei as applied to claim 1 above, and further in view of Wang (US2021/0081109), hereinafter Wang’109.
Regarding claim 7, the combination of Cho teaches all the features with respect to claim 1 as outlined above. The combination of Cho does not explicitly teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine, at a first time, a first operating temperature of the memory system, wherein the temperature metric comprises the first operating temperature; determine, at a second time that is prior to the first time, a second operating temperature of the memory system, wherein a second temperature metric comprises the second operating temperature; and compare the temperature metric to the second temperature metric based at least in part on determining the temperature metric, as claimed.
However, the combination of Cho in view of Wang’109 teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine, at a first time, a first operating temperature of the memory system, wherein the temperature metric comprises the first operating temperature; determine, at a second time that is prior to the first time, a second operating temperature of the memory system, wherein a second temperature metric comprises the second operating temperature; and compare the temperature metric to the second temperature metric based at least in part on determining the temperature metric (Wang’109, [0095], When the temperature acquired from the temperature sensor 15 changes, for example, when the new current temperature acquired from the temperature sensor 15 and the temperature acquired immediately before are different from each other by a threshold value or more, the PHY parameter control unit 123 acquires a PHY parameter set corresponding to the new current temperature).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Wang’109 to compare a current temperature from a temperature sensor with a temperature acquired immediately before and take actions if the difference between the two temperature values satisfy a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Wang’109 because it improves efficiency and reliability of the storage system disclosed in the combination of Cho by monitoring operational temperatures and taking actions when the operational temperatures satisfy a threshold limit.
Regarding claim 8, the combination of Cho teaches all the features with respect to claim 7 as outlined above. The combination of Cho does further teaches the memory system of claim 7, wherein determining whether a difference between the temperature metric and the second temperature metric satisfies the threshold (Wang’109, [0095], When the temperature acquired from the temperature sensor 15 changes, for example, when the new current temperature acquired from the temperature sensor 15 and the temperature acquired immediately before are different from each other by a threshold value or more, the PHY parameter control unit 123 acquires a PHY parameter set corresponding to the new current temperature).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Wang’109 to compare a current temperature from a temperature sensor with a temperature acquired immediately before and take actions if the difference between the two temperature values satisfy a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Wang’109 because it improves efficiency and reliability of the storage system disclosed in the combination of Cho by monitoring operational temperature and taking actions when the operational temperature satisfies a threshold limit.
Regarding claim 9, the combination of Cho teaches all the features with respect to claim 7 as outlined above. The combination of Cho further teaches the memory system of claim 7, wherein the processing circuitry is further configured to cause the memory system to: determine that the second temperature metric is different from the temperature metric, wherein determining whether the temperature metric satisfies the threshold is based at least in part on determining that the second temperature metric is different from the temperature metric (Wang’109, [0095], When the temperature acquired from the temperature sensor 15 changes, for example, when the new current temperature acquired from the temperature sensor 15 and the temperature acquired immediately before are different from each other by a threshold value or more, the PHY parameter control unit 123 acquires a PHY parameter set corresponding to the new current temperature).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Wang’109 to compare a current temperature from a temperature sensor with a temperature acquired immediately before and take actions if the difference between the two temperature values satisfy a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Wang’109 because it improves efficiency and reliability of the storage system disclosed in the combination of Cho by monitoring operational temperature and taking actions when the operational temperature satisfies a threshold limit.
Claim(s) 12, 14-15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US2024/0126663), hereinafter Cho in view of Hadar et al. (US2022/0014400), hereinafter Hadar, and further in view of Tan et al. (WO 2022/226783), hereinafter Tan, Hansson et al. (US2018/0089079), hereinafter Hansson, and Wei et al. (US2024/0144982), hereinafter Wei.
Regarding claim 12, Cho teaches a memory system, comprising:
one or more memory devices (Cho, [0028], memory devices 13; Fig.1); and
processing circuitry (Cho, [00028], controller 12; Fig.1) coupled with the one or more memory devices and configured to cause the memory system to:
establish, while the memory system operates according to a first power state, a communications link between the memory system and a host system , the communications link based at least in part on a first resistor termination scheme associated with a first protocol layer (Cho, [0032], The controller 12 may include a PCIe controller (PCTR) 18 that establishes a link between an external host and a PCIe interface; [0033], the PCIe controller 18 may proceed with a link-up process of establishing a link between an external host and the storage device 10 by determining values of PHY parameters that may be configured in the physical layer; [0041], In order to exchange data with each other, when the power of the system 20 is turned on and the power is supplied to the host 30, the storage device 40, and the graphic processing device 50, the link-up process configuring the links between the interfaces 31A, 31B, 41, and 51 may be executed);
determine whether a temperature metric of the memory system satisfies a threshold based on a power state of the memory system changing from the first power state to a second power state (Cho, [0042], when a device connected to the PCIe interface is changed or the external temperature and the power are changed, the performance of the system 20 may deteriorate; [0045], internal temperature of the storage device);
enable a second resister termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold; and
communicate, while operating according to the second power state and based at least in part on the temperature metric satisfying the threshold, data from the memory system using the communications link based at least in part on the second resistor termination scheme associated with the first protocol layer, wherein the first resistor termination scheme is different than the second resistor termination scheme (Cho, [0042]; [0043], when … or the external temperature and the power are changed, by changing the PHY parameters as needed … the PCIe interface may be controlled in an optimal condition; [0077], In addition, as at least one of the PHY parameters is configured with a different value, at least one of the data signals DATA0 and DATA1 transmitted through the same lane have different waveforms).
Cho teaches changes in temperature and power trigger a first PHY parameter to be adjusted to a second PHY parameter, nevertheless, Cho does not explicitly teach determining a temperature metric satisfies a threshold based on changes in power state and the PHY parameter is a resistor termination scheme, as claimed. Cho also does not explicitly teach enable a second resister termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold, as claimed.
However, Cho in view of Hadar teaches temperature metric of memory system satisfying the threshold (Hadar, [0024], When the temperature is below a certain threshold, the VGA gain is set to a low value; [0030], if the current die temperature is in the mid-range, between a low threshold and a high threshold, the VGA gain initial target will be for a mid-gain value; [0020]; [0021], FIG. 2 shows receiver equalization components 200 implemented in a receiver PHY (Physical Layer) that are used to establish initial link equalization parameters and subsequently adjust the link signals to adapt to changes in the platform temperature).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cho to incorporate teachings of Hadar to determine changes in temperature by comparing the temperature with a threshold value. A person of ordinary skill in the art would have been motivated to combine the teachings of Cho with Hadar because it improves efficiency of the storage system disclosed in Cho by defining a clear limit in order to detect abnormal conditions quickly.
The combination of Cho does not explicitly teach a first power state is changed to a second power state, a first resistor termination scheme and a second resistor termination scheme are associated with a physical layer (PHY), and enable a second resister termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold, as claimed.
However, the combination of Cho in view of Tan teaches determine whether a temperature metric of the memory system satisfies a threshold based on a power state of the memory system changing from the first power state to a second power state (Tan, [0053], deactivated state … low-power state mode … hibernate state; [0062], At 425, a voltage transition occurs; [0064], At 430, a second temperature is determined; [0064], At 435, whether the second temperature exceeds a second temperature threshold is determined; Hadar, [0024], [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate changes of Tan to determine whether a temperature of a memory system satisfies a threshold after power state of the memory system changed from a first power state to a second power state. If the temperature of the memory system satisfies a threshold at a power state, PHY parameters can be adjusted. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Tan because it improves efficiency of the storage system disclosed in the combination of Cho by allowing dynamic thermal operations based on different power states.
The combination of Cho does not explicitly teach a first resistor termination scheme and a second resistor termination scheme are associated with a physical layer (PHY), and enable a second resister termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold, as claimed.
However, the combination of Cho in view of Hansson and Wei teaches first resistor termination scheme associated with a first protocol layer; a second resistor termination scheme associated with the first protocol layer (Hansson, [0106]);
enable a second resister termination scheme associated with the first protocol layer based at least in part on determining that the temperature metric satisfies the threshold (Hansson, [0047], perform a termination setting operation to configure termination components within the associated memory module dependent on whether a currently processed command identifies the direct data transfer or identifies a transfer to be performed between the memory controller and the associated memory module; [0092], Over time, drift can be introduced into the signals propagating over the connection between the physical layer interface 35 and the portion of memory 40 due to a variety of factors, for example changes in operating temperature and voltage, etc. Hence, periodically a training operation may need to be performed on the physical layer interface 35 in order to update the configuration of the synchronisation control block 150 … When a threshold is exceeded, then the training operation could be initiated; [0106]; [0121]; Fig.12; Wei, [0057], providing an ODT configuration value to an ODT configuration circuit. Generally, an ODT Rtt circuit block may provide one of several possible termination resistances (Rtt). The termination resistance provided by the ODT Rtt circuit block may be determined by enabling and disabling various pathways within the ODT Rtt circuit block, so as to “program” or “configure” the ODT Rtt circuit block to effectively provide the desired termination resistance);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Hansson to initiate a training/calibration operation associated with termination resistor setting in response to determining that operating temperature exceeds a threshold. The updated termination resistor settings are communicated across physical connections. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Hansson because it improves efficiency and accuracy of the storage system disclosed in the combination of Cho by ensuring that synchronized communication is maintained across the various paths used during data transfer (Hansson, [0045]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Cho to incorporate teachings of Wei to enable/disable various pathways of a termination resistor circuit in order to provide a desired termination resistance/impedance. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Cho with Wei because it improves efficiency and accuracy of the storage system disclosed in the combination of Cho by providing a desired termination resistance/ impedance using various resister termination scheme.
Regarding claim 14, the claim has similar limitations as claim 3 and is rejected for the similar reasons.
Regarding claim 15, the claim has similar limitations as claim 6 and is rejected for the similar reasons.
Regarding claim 19, the claim has similar limitations as claim 10 and is rejected for the similar reasons.
Regarding claim 20, the claim has similar limitations as claim 11 and is rejected for the similar reasons.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cho, Hadar, Tan, Hansson, and Wei as applied to claim 12 above, and further in view of Noh et al. (US2021/0216223), hereinafter Noh.
Regarding claim 13, the claim has similar limitations as claim 2 and is rejected for the similar reasons.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cho, Hadar, Tan, Hansson, and Wei as applied to claim 12 above, and further in view of Wang (US2021/0081109), hereinafter Wang’109.
Regarding claim 16, the claim has similar limitations as claim 7 and is rejected for the similar reasons.
Regarding claim 17, the claim has similar limitations as claim 8 and is rejected for the similar reasons.
Regarding claim 18, the claim has similar limitations as claim 9 and is rejected for the similar reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NANCI N WONG/Primary Examiner, Art Unit 2137
Prosecution Insights