DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 6/17/2026.
Claims 1, 17, and 20 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
The text of those sections of Title 35, U. S. Code not included in this action can be found in a prior Office action.
Claim Rejections - 35 USC § 112
The Examiner thanks Applicant for amending the claims to cure the rejections of claims 1-20 under 35 U.S.C. §112(b) made in the non-final Office action dated 3/17/2026 and therefore respectfully withdraws the rejections of claims 1-20 under 35 U.S.C. §112(b) made therein.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix; and obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…” (independent claim 1, lines 3-7).
The Examiner is uncertain if the recitation of “obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix” means any of the following possible interpretations:
both “a check expression based on a codeword to be decoded in a current iteration” and “a check matrix” are obtained;
“a check expression” is obtained “based on a codeword to be decoded in a current iteration and a check matrix”;
“a check expression” that is “based on” both “a codeword to be decoded in a current iteration and a check matrix” is obtained; or
some other possible, unconsidered interpretation.
The Examiner is also uncertain if the recitation of “obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression” means any of the following possible interpretations:
“a check expression weight” that is “based on the check expression” in which “the check expression weight comprises a quantity of binary one values in the check expression” is obtained;
“a check expression weight” is obtained based on “a quantity of binary one values in the check expression”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix; and obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…” to read “…obtain both a check expression that is based on a codeword to be decoded in a current iteration and a check matrix; and obtain a check expression weight that is based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…”
Dependent claims 2-16, which ultimately depend from independent claim 1, are rejected for carrying the same deficiencies.
Claims 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 17 recites “…obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix; and obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…” (independent claim 17, lines 5-9). Independent claim 17 also recites “…a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the” (independent claim 17, lines 15-18).
The Examiner is uncertain if the recitation of “obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix” means any of the following possible interpretations:
both “a check expression based on a codeword to be decoded in a current iteration” and “a check matrix” are obtained;
“a check expression” is obtained “based on a codeword to be decoded in a current iteration and a check matrix”;
“a check expression” that is “based on” both “a codeword to be decoded in a current iteration and a check matrix” is obtained; or
some other possible, unconsidered interpretation.
The Examiner is also uncertain if the recitation of “obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression” means any of the following possible interpretations:
“a check expression weight” that is “based on the check expression” in which “the check expression weight comprises a quantity of binary one values in the check expression” is obtained;
“a check expression weight” is obtained based on “a quantity of binary one values in the check expression”; or
some other possible, unconsidered interpretation.
Finally, the Examiner notes that the “the” concluding this recitation lacks an object, so the Examiner is uncertain what the “the” is intended to reference.
For the sake of examination, the Examiner has interpreted “…obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix; and obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…” to read “…obtain both a check expression that is based on a codeword to be decoded in a current iteration and a check matrix; and obtain a check expression weight that is based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…”
In addition, for the sake of examination, the Examiner has interpreted “…a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the” to read “…a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the processor.”
Dependent claims 18-19, which ultimately depend from independent claim 17, are rejected for carrying the same deficiencies.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 20 recites “…obtaining a check expression based on a codeword to be decoded in a current iteration and a check matrix; and obtaining a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…” (independent claim 20, lines 6-10).
The Examiner is uncertain if the recitation of “obtaining a check expression based on a codeword to be decoded in a current iteration and a check matrix” means any of the following possible interpretations:
both “a check expression based on a codeword to be decoded in a current iteration” and “a check matrix” are obtained;
“a check expression” is obtained “based on a codeword to be decoded in a current iteration and a check matrix”;
“a check expression” that is “based on” both “a codeword to be decoded in a current iteration and a check matrix” is obtained; or
some other possible, unconsidered interpretation.
The Examiner is also uncertain if the recitation of “obtaining a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression” means any of the following possible interpretations:
“a check expression weight” that is “based on the check expression” in which “the check expression weight comprises a quantity of binary one values in the check expression” is obtained;
“a check expression weight” is obtained based on “a quantity of binary one values in the check expression”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…obtaining a check expression based on a codeword to be decoded in a current iteration and a check matrix; and obtaining a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…” to read “…obtaining both a check expression that is based on a codeword to be decoded in a current iteration and a check matrix; and obtaining a check expression weight that is based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression…”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over USPGPUB 2023/0308114 (“Kaynak”) in view of USPGPUB 2016/0011934 (“Hsu”).
As per claim 1, Kaynak substantially teaches a decoder (Kaynak, Abstract; and paragraph 0001), comprising:
a first processing circuit configured to: obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix: (Kaynak, Abstract; FIG. 2; and paragraph 0032-0040, where the bit flipping decoder of Kaynak uses a Low-Density Parity Check (LDPC) code to encode data for error correction. The system of Kaynak receives a codeword from a memory device; the received codeword comprises both data bits and parity check bits. The Examiner notes that parity check bits are a check expression that is used for error correction for the received codeword. In addition, soft information indicating a confidence level associated with bits of the received codeword (i.e., check expression weights that are based on the codeword) may be included. Based on parity checks, a syndrome matrix indicating passed and failed parity checks (i.e., a check matrix) may be used during iterations of the error correction process. Kaynak therefore substantially teaches a first processing circuit configured to: obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix);
a second processing circuit configured to obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration: (Kaynak, Abstract; FIG. 2; and paragraph 0045, where the system of Kaynak may also process energy information associated with the received codeword in conjunction with the soft information confidence level to flip bits based on whether errors are detected. Kaynak therefore substantially teaches a second processing circuit configured to obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration);
a processor configured to determine a flipping threshold in the current iteration based on a changing state of the check expression weight: (Kaynak, Abstract; FIG. 2; and paragraphs 0041-0043 and 0054, where a bit flipping threshold for the energy information is used to determine whether or not a given bit should be flipped. Kaynak therefore substantially teaches a processor configured to determine a flipping threshold in the current iteration based on a changing state of the check expression weight); and
a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the processor: (Kaynak, Abstract; FIG. 2; and paragraph 0053, where zero or more bits of the received codeword are flipped based on the energy information. This means that a circuit to flip bits must be used to flip the bits. Kaynak therefore substantially teaches a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the processor).
Kaynak does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Hsu teaches decoding method, memory control circuit unit and memory storage device.
As per claim 1, Hsu particularly teaches:
obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression: (Hsu, Abstract; FIG. 17; and paragraphs 0008-0012, 0081, and 0108-0111, where the system of Hsu obtains reliability information and uses the reliability information with balance information to obtain a weight corresponding to a first bit among a set of bits and a syndrome (i.e., a check expression weight). The syndrome of Hsu is used for error checking by counting a number of bits that have a value of “1” (i.e., a quantity of binary one values in the check expression). Hsu therefore particularly teaches obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hsu and Kaynak before them before the instant application was effectively filed, to modify the system of Kaynak to include the principles of Hsu of using a syndrome and parity of a check expression in order to detect and correct errors.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing decoding techniques that effectively improve a correcting capability of decoding (Hsu, paragraphs 0007-0008).
As per claim 17, Kaynak substantially teaches a memory system (Kaynak, FIG. 1), comprising:
a memory configured to output read data: (Kaynak, Abstract; FIG. 1, reference numerals 110, 130, and 140; and paragraphs 0009-0010 and 0020, where memory subsystem 110 includes memory devices 130 and 140 used to store data that can be read in response to host requests. Kaynak therefore substantially teaches a memory configured to output read data); and
a decoder comprising: a first processing circuit configured to: obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix: (Kaynak, Abstract; FIG. 1, reference numerals 110, 113, 115, 117, 119, 130, and 140; FIG. 2; and paragraphs and 0031-0040, where a bit flipping decoder of memory subsystem controller 115 of Kaynak uses processing circuitry (i.e., a first processing circuit and a second processing circuit) to decode codewords. In addition, (Kaynak, Abstract; FIG. 2; and paragraph 0032-0040) teaches where the bit flipping decoder of Kaynak uses a Low-Density Parity Check (LDPC) code to encode data for error correction. The system of Kaynak receives a codeword from a memory device; the received codeword comprises both data bits and parity check bits. The Examiner notes that parity check bits are a check expression that is used for error correction for the received codeword. In addition, soft information indicating a confidence level associated with bits of the received codeword (i.e., check expression weights that are based on the codeword) may be included. Based on parity checks, a syndrome matrix indicating passed and failed parity checks (i.e., a check matrix) may be used during iterations of the error correction process. Kaynak therefore substantially teaches a decoder comprising: a first processing circuit configured to: obtain a check expression based on a codeword to be decoded in a current iteration and a check matrix);
a second processing circuit configured to obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration: (Kaynak, Abstract; FIG. 2; and paragraph 0045, where the system of Kaynak may also process energy information associated with the received codeword in conjunction with the soft information confidence level to flip bits based on whether errors are detected. Kaynak therefore substantially teaches a second processing circuit configured to obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration);
a processor configured to determine a flipping threshold in the current iteration based on a changing state of the check expression weight: (Kaynak, Abstract; FIG. 2; and paragraphs 0041-0043 and 0054, where a bit flipping threshold for the energy information is used to determine whether or not a given bit should be flipped. Kaynak therefore substantially teaches a processor configured to determine a flipping threshold in the current iteration based on a changing state of the check expression weight); and
a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the: (Kaynak, Abstract; FIG. 2; and paragraph 0053, where zero or more bits of the received codeword are flipped based on the energy information. This means that a circuit to flip bits must be used to flip the bits. Kaynak therefore substantially teaches a bit flipping circuit configured to output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the).
Kaynak does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Hsu teaches decoding method, memory control circuit unit and memory storage device.
As per claim 17, Hsu particularly teaches:
obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression: (Hsu, Abstract; FIG. 17; and paragraphs 0008-0012, 0081, and 0108-0111, where the system of Hsu obtains reliability information and uses the reliability information with balance information to obtain a weight corresponding to a first bit among a set of bits and a syndrome (i.e., a check expression weight). The syndrome of Hsu is used for error checking by counting a number of bits that have a value of “1” (i.e., a quantity of binary one values in the check expression). Hsu therefore particularly teaches obtain a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hsu and Kaynak before them before the instant application was effectively filed, to modify the system of Kaynak to include the principles of Hsu of using a syndrome and parity of a check expression in order to detect and correct errors.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing decoding techniques that effectively improve a correcting capability of decoding (Hsu, paragraphs 0007-0008).
As per claim 20, Kaynak substantially teaches an operating method for a memory system, the operating method (Kaynak, FIG. 1 and FIG. 2) including:
reading data using a memory: (Kaynak, Abstract; FIG. 1, reference numerals 110, 130, and 140; and paragraphs 0009-0010 and 0020, where memory subsystem 110 includes memory devices 130 and 140 used to store data that can be read in response to host requests. Kaynak therefore substantially teaches reading data using a memory); and
decoding a codeword to be decoded in the read data using a decoding method, the decoding comprising: (Kaynak, Abstract; FIG. 1, reference numerals 110, 113, 115, 117, 119, 130, and 140; and paragraphs and 0031-0035, where a bit flipping decoder of memory subsystem controller 115 of Kaynak uses processing circuitry (i.e., a first processing circuit and a second processing circuit) to decode codewords. Kaynak therefore substantially teaches decoding a codeword to be decoded in the read data using a decoding method comprising);
obtaining a check expression based on a codeword to be decoded in a current iteration and a check matrix: (Kaynak, Abstract; FIG. 2; and paragraph 0032-0040, where the bit flipping decoder of Kaynak uses a Low-Density Parity Check (LDPC) code to encode data for error correction. The system of Kaynak receives a codeword from a memory device; the received codeword comprises both data bits and parity check bits. The Examiner notes that parity check bits are a check expression that is used for error correction for the received codeword. In addition, soft information indicating a confidence level associated with bits of the received codeword (i.e., check expression weights that are based on the codeword) may be included. Based on parity checks, a syndrome matrix indicating passed and failed parity checks (i.e., a check matrix) may be used during iterations of the error correction process. Kaynak therefore substantially teaches obtaining a check expression based on a codeword to be decoded in a current iteration and a check matrix);
obtaining energy of the codeword to be decoded in the current iteration based on the check matric, the check expression, and a flipping state of the codeword to be decoded in the current iteration: (Kaynak, Abstract; FIG. 2; and paragraph 0045, where the system of Kaynak may also process energy information associated with the received codeword in conjunction with the soft information confidence level to flip bits based on whether errors are detected. Kaynak therefore substantially teaches obtaining energy of the codeword to be decoded in the current iteration based on the check matric, the check expression, and a flipping state of the codeword to be decoded in the current iteration);
determining a flipping threshold in the current iteration, based on a changing state of the check expression weight: (Kaynak, Abstract; FIG. 2; and paragraphs 0041-0043 and 0054, where a bit flipping threshold for the energy information is used to determine whether or not a given bit should be flipped. Kaynak therefore substantially teaches determining a flipping threshold in the current iteration, based on a changing state of the check expression weight); and
outputting a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration: (Kaynak, Abstract; FIG. 2; and paragraph 0053, where zero or more bits of the received codeword are flipped based on the energy information. This means that a circuit to flip bits must be used to flip the bits. Kaynak therefore substantially teaches outputting a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration).
Kaynak does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Hsu teaches decoding method, memory control circuit unit and memory storage device.
As per claim 20, Hsu particularly teaches:
obtaining a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression: (Hsu, Abstract; FIG. 17; and paragraphs 0008-0012, 0081, and 0108-0111, where the system of Hsu obtains reliability information and uses the reliability information with balance information to obtain a weight corresponding to a first bit among a set of bits and a syndrome (i.e., a check expression weight). The syndrome of Hsu is used for error checking by counting a number of bits that have a value of “1” (i.e., a quantity of binary one values in the check expression). Hsu therefore particularly teaches obtaining a check expression weight based on the check expression, wherein the check expression weight comprises a quantity of binary one values in the check expression).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Hsu and Kaynak before them before the instant application was effectively filed, to modify the system of Kaynak to include the principles of Hsu of using a syndrome and parity of a check expression in order to detect and correct errors.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by implementing decoding techniques that effectively improve a correcting capability of decoding (Hsu, paragraphs 0007-0008).
Response to Arguments
In the Remarks dated 6/17/2026, Applicant substantially argues:
Kaynak fails to teach or suggest the claimed combination of features of the amended claims of the instant application.
Applicant’s arguments dated 6/17/2026 have been fully considered, but they are moot in view of the new grounds of rejection that were necessitated by Applicant’s amendments to the claims. The Examiner notes that the new Hsu reference, in combination with Kaynak, clearly teaches the limitations added via amendment. The Examiner further notes that the new grounds of rejection were necessitated by Applicant’s amendments to the claims.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
Prosecution Insights