DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi et al. (US Pat. 10,693,460).
Regarding claims 10 and 17, Fig. 5A of Takahashi discloses a method and apparatus comprising:
a first logic level driver [combination of 142 and 143] coupled to a data terminal [DQ], the first logic level driver configured to provide a first logic level voltage [voltage on drain of transistor 142] when activated by output driver data control signals [signal output by 126];
a second logic level driver [combination of 144 and 145] coupled to the data terminal [DQ], the second logic level driver configured to provide a second logic level voltage [ground] when activated by the output driver data control signals [signal output by 128]; and
a third logic level driver [combination of 154 and 152] coupled to the data terminal [DQ], the third logic level driver configured to provide a third logic level voltage [voltage output source of 142] when activated by the output driver data control signals [SWPU],
wherein one of the first, second, and third logic level drivers is activated at a time [each driver provides different voltage to data terminal at different time. Therefore, it is inherent that one of the driver is activated at a time], and
wherein the third logic level voltage has a magnitude between [since voltage at the drain of 154 is a drop voltage from 142, it is smaller than the voltage at the first level] the first [high] and second logic level [low] voltages.
Regarding claim 11, Fig. 5A of Takahashi discloses wherein activating the high logic level driver comprises: receiving a first data output driver data control signal [signal output by 126] and a first voltage [voltage at drain of 142]; and activating a p-channel transistor [142] coupled to the high logic level driver to provide the first voltage to a resistance [143] coupled to the data terminal [DQ] to provide the high logic level voltage to the terminal.
Regarding claim 12, Fig. 5A of Takahashi discloses wherein activating the low logic level driver comprises: receiving a second data output driver data control signal [signal output by 128] and a second voltage [ground voltage connects to source of 144]; and activating an n-channel transistor [144] coupled to the low logic level driver to provide the second voltage to a resistor [145] coupled to the data terminal to provide the low logic level voltage [ground level].
Regarding claim 13, Fig. 5A of Takahashi discloses wherein activating the intermediate logic level driver comprises: receiving a third output driver data control signal [SWPU] and a third voltage [voltage outputs by source of transistor 142]; activating a p-channel transistor [154] coupled to the intermediate logic level driver to provide the third voltage [voltage at source of transistor 142] to a first resistor [152] coupled to the data terminal [DQ]; and activating an n-channel transistor [154B in Fig. 5B] to provide the third voltage to a second resistor [152B, Fig. 5B] coupled to the data terminal.
Regarding claim 14, Fig. 5A of Takahashi discloses receiving the first voltage [high voltage at drain of 142] and a cutoff control signal [signal outputs by 126] at a cutoff circuit, wherein the third voltage is cutoff [signal SWPU] when the cutoff circuit is activated by the cutoff control signal.
Regarding claim 15, Fig. 5A of Takahashi discloses transitioning an output data signal from a first logic level voltage [high] to a second logic level voltage [low], wherein the transitioning comprises: deactivating one of the low logic level driver the high logic level driver, and the intermediate logic level driver corresponding to the first logic level voltage [if low level voltage is connected to DQ, then first and third drivers are deactivated]; and activating another one of the low logic level driver, the high logic level driver, and the intermediate logic level driver corresponding to the second logic level voltage [intermediate logic level driver will be activated].
Regarding claim 16, Fig. 5A of Takahashi discloses maintaining a remaining one of the low logic level driver, the high logic level driver, and the intermediate logic level driver [maintaining third driver 154] not corresponding to the first logic level voltage or the second logic level voltage.
Regarding claim 18, Fig. 5A of Takahashi discloses wherein the first logic level driver [142] is configured to be activated responsive to an active first control signal of the output driver data control signals [signal output by 126]; the second logic level driver [144] is configured to be activated responsive to an active second control signal of the output driver data control signals [signal outputs by 128]; and the third logic level driver configured to be activated responsive to an active third control signal and an active fourth control signal of the output driver data control signals [SWPU and SWPD], the third and fourth control signals are complementary.
Regarding claim 19, Fig. 5A of Takahashi discloses wherein the third logic level driver comprises a first resistance [152] and a first middle driver [154] coupled to the first resistance [152] and further comprises a second resistance [152B, Fig. 5B] and a second middle driver [154B, Fig. 5B] coupled to the second resistance [152B], the first middle driver configured to be activated responsive to an active high third control signal [SWPU<0>] and the second middle driver configured to be activated responsive to an active low fourth control signal [SWPU<1>].
Regarding claim 20, Fig. 5A of Takahashi discloses wherein the first middle driver is further coupled to a cutoff circuit [circuit that generates SWPU signal to turn off the driver], wherein the third logic level voltage is cutoff to the first middle driver when the cutoff circuit is activated [when the driver is selected to be off], and wherein the third logic level voltage [voltage provided by transistor 154 to data terminal DQ] is provided to the first middle driver when the cutoff circuit is deactivated.
Allowable Subject Matter
Claims 1-9 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 1-9, the prior art does not teach or suggest either alone or in combination an output driver, comprising: third and fourth transistors coupled to the data terminal, and the third and fourth transistors configured to be provided a third level voltage, wherein a voltage corresponding to the third level voltage is provided by the third and fourth transistors being activated and the first transistor and the second transistor being deactivated.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
