DETAILED ACTION
This office action is in response to the application filed on 02/13/2025. Claims 1-5 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 02/13/2025 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/13/2025 and 08/25/2025 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by PECHTOLD MICHAEL et al. (WO2014202282A1, hereinafter PECHTOLD MICHAEL)
Claim 1, PECHTOLD MICHAEL teaches an inverter device (e.g., see Fig. 4-6), comprising: an interconnect substrate having a first interconnect layer (e.g., L2) and a second interconnect layer (e.g., L1); and a plurality of transistors (4' and 5') arranged in a middle layer between the first interconnect layer and the second interconnect layer, each having a source (e.g., 4b', 5b') on one face and a drain (e.g., 4c',5c') on the other face, wherein the plurality of transistors include a first transistor (e.g., 4') placed with the one face facing the first interconnect layer and a second transistor (e.g., 5') placed with the other face facing the first interconnect layer, and the source (e.g., 4b') of the first transistor and the drain (e.g., 5c') of the second transistor are connected through a first interconnect in the first interconnect layer (e.g., 4b' and 5c' are connected to 3' formed in L2, see Fig. 4).
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4-5 are allowable.
The following is a statement of reasons for the indication of allowable subject matters:
For claims 2-3, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the plurality of transistors include a third transistor placed with the one face facing the first interconnect layer, and the source of the first transistor, the drain of the second transistor, and the source of the third transistor are connected through the first interconnect”.
For claims 4-5, the prior art does not disclose or suggest, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a third transistor placed with the one face facing the first interconnect layer, its source being connected to an output interconnect in the first interconnect layer and its drain connected to the first interconnect, a fourth transistor placed with the one face facing the first interconnect layer, its source being connected to a third interconnect in the first interconnect layer and its drain connected to the output interconnect, a fifth transistor placed with the one face facing the first interconnect layer, its source being connected to the third interconnect and its drain connected to the second interconnect, and a sixth transistor placed with the other face facing the first interconnect layer, its drain being connected to the third interconnect”.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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