DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.KR10-2024-0053497 filed on 04/22/2024 and KR10-2024-0134063, filed on 10/02/2024.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Segev et al. (2023/0376244), hereinafter Segev in view of Call et al. (US8,924,629), hereinafter Call.
Regarding claims 1 and 13, taking claim 1 as exemplary, Segev teaches a data storage device (Segev, [0022], data storage device 106) comprising:
a memory device (Segev, [0024], The data storage device 106 includes … NVM 110; Fig.1); and
a memory controller (Segev, [0024], The data storage device 106 includes a controller 108) configured to;
receive one or more write commands (Segev, [0044], the controller receives a write command at 502) from an external device (Segev, [0031], a write command from the host device 104),
combine the one or more write commands based on size information of write data corresponding to the one or more write commands (Segev, [0045]-[0046]; [0049], The pre-aggregation module is configured to aggregate write commands for which data associated with the write commands individually do not match page size),
transmit, to the memory device, a program command corresponding to the combined write command (Segev, [0043], The pre-aggregation module functions as a buffer to accumulate mis-aligned write commands to ensure data is ultimately written to the memory device; [0046], then a determination is made at 714 whether the data associated with the commands that are in the pre-aggregation module collectively are aligned with the memory device (e.g., NAND) size. If aligned, then the data can be fetched at 706 and scheduled to be written to the memory device at 708; Note – an instruction sent to memory device to write data is considered as a program command), and
receive, from the external device, write data related to the combined write command before or after generating the program command after combining the one or more write commands (Segev, [0032], The write aggregation module 208 is responsible for bringing enough data from the host device; [0045], If the data associated with the write command will not be aligned with the memory device (e.g., NAND) size at 704, then the write command is placed in the pre-aggregation module at 706. Other write commands may already be present in the pre-aggregation module 706; [0046], then a determination is made at 714 whether the data associated with the commands that are in the pre-aggregation module collectively are aligned with the memory device (e.g., NAND) size. If aligned, then the data can be fetched at 706 ).
Segev does not explicitly teach generating a program command after combining the one or more write commands, as claimed.
However, Segev in view of Call teaches generating a program command after combining the one or more write commands (Call, col.4, lines 1-24, an example is shown for a controller in a storage device to combine two commands received from a host … two 4-Kb write commands are combined into one 8-Kb write command to a storage array with 8-Kb pages.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Segev to incorporate teachings of Call to combine multiple write command into one write command by a storage controller. A person of ordinary skill in the art would have been motivated to combine the teachings of Segev with Call because it improves efficiency of the storage system disclosed in Segev by transmitting a single I/O command instead of multiple I/O commands.
Claim 13 is similar limitations as claim 1 and they are rejected for the similar reasons.
Regarding claims 2 and 14, taking claim 2 as exemplary, the combination of Segev teaches all the features with respect to claim 1 as outlined above. The combination of Segev further teaches the data storage device according to claim 1, wherein the memory controller combines the one or more write commands so that the combined write command corresponds to a unit program size that is a size of data that are programmed into the memory device when the memory device performs a single program operation (Segev, [0032], The write aggregation module 208 is responsible for bringing enough data from the host device to fill at least an entire memory device page (e.g., a NAND page); [0044], A determination is made, prior to retrieving the data associated with the write command, whether the data associated with the write command will be aligned with the memory device (e.g., NAND) size at 704. If the data will be aligned, then the data is fetched at 706 and writing the data to the memory device is scheduled at 708).
Claim 14 is similar limitations as claim 2 and they are rejected for the similar reasons.
Claim(s) 3, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Segev and Call as applied to claims 1 and 13 respectively above, and further in view of Bai et al. (US2024/0232106), hereinafter Bai.
Regarding claims 3 and 15, taking claim 3 as exemplary, the combination of Segev teaches all the features with respect to claim 1 as outlined above. The combination of Segev does not explicitly teach the data storage device according to claim 1, wherein the memory controller receives the write data after generating the program command when a workload is determined to be a first workload based on a command that is transmitted by the external device, as claimed.
However, the combination of Segev in view of Bai teaches the data storage device according to claim 1, wherein the memory controller receives the write data after generating the program command when a workload is determined to be a first workload based on a command that is transmitted by the external device (Segev, [0040], A determination is made at 518 whether more data has been fetched than the required queue depth to meet performance bandwidth plus some H overhead. If FD is greater than FC+H at 518, then the mode is changed to fetch after at 520 and the controller waits for the next write command at 510. If FD is not greater than FC+H at 518, then the mode remains in fetch first and the controller waits for the next write command at 510; [0049], The pre-aggregation module is configured to aggregate write commands for which data associated with the write commands individually do not match page size; Bai, [0043], in various embodiments the CDR server can produce the merged I/O request by appending expected I/O requests to an I/O request that the CDR server receives).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Segev to incorporate teachings of Bai to append a new write command to an existing write command when the write commands need to be merged/combined. As such, fetching write data from a host is be performed after a merge command is generated and the fetching of write data is performed based on the corresponding fetch depth. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Segev with Bai because it improves performance of the storage system disclosed in the combination of Segev by generating a merged I/O command as soon as a last I/O command is received and appended.
Claim 15 is similar limitations as claim 3 and they are rejected for the similar reasons.
Regarding claim 18, the combination of Segev teaches all the features with respect to claim 13 as outlined above. The combination of Segev does not explicitly teach the operating method according to claim 13, further comprising: determining, by the memory controller, a workload based on a command that is transmitted by the external device; and generating the program command after receiving the write data when the workload is determined to be a second workload, as claimed.
However, the combination of Segev in view of Bai teaches the operating method according to claim 13, further comprising: determining, by the memory controller, a workload based on a command that is transmitted by the external device; and generating the program command after receiving the write data when the workload is determined to be a second workload (Segev, [0040], A determination is made at 518 whether more data has been fetched than the required queue depth to meet performance bandwidth plus some H overhead. If FD is greater than FC+H at 518, then the mode is changed to fetch after at 520 and the controller waits for the next write command at 510. If FD is not greater than FC+H at 518, then the mode remains in fetch first and the controller waits for the next write command at 510; [0049], The pre-aggregation module is configured to aggregate write commands for which data associated with the write commands individually do not match page size; Bai, [0043], in various embodiments the CDR server can produce the merged I/O request by appending expected I/O requests to an I/O request that the CDR server receives).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Segev to incorporate teachings of Bai to append a new write command to an existing write command when write commands need to be merged/combined. As such, fetching write data from a host is performed before a merge command is generated and the fetching of write data is based on a corresponding fetch depth. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Segev with Bai because it improves performance of the storage system disclosed in the combination of Segev by generating a merged I/O command when a new I/O command is received.
Claim(s) 5, 17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Segev, Call, and Bai as applied to claims 3, 15, and 18 respectively above, and further in view of Kanno et al. (US2025/0094345), hereinafter Kanno.
Regarding claims 5, 17, and 20, taking claim 5 as exemplary, the combination of Segev teaches all the features with respect to claim 3 as outlined above. The combination of Segev does not explicitly teach the data storage device according to claim 3, wherein the memory controller transmits a program completion signal to the external device after receiving the write data, as claimed.
However, the combination of Segev in view of Kanno teaches the data storage device according to claim 3, wherein the memory controller transmits a program completion signal to the external device after receiving the write data (Kanno, [0090]; [0092], The write control unit 521 executes … completion response notification processing; [0097], The completion response notification processing is processing of notifying the host 2 of a completion response indicating completion of processing of the received write command. The completion response notification processing may be executed, for example, at a time point when the write data is received from the host 2; Fig.1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Segev to incorporate teachings of Kanno to send a program completion message when the write data is received from a host. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Segev with Kanno because it improves efficiency of the storage system disclosed in the combination of Segev by providing processing status of I/O commands/requests to requestors.
Claims 17 and 20 are similar limitations as claim 5 and they are rejected for the similar reasons.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Segev and Call as applied to claim 1 above, and further in view of Cao et al. (US2022/0317905), hereinafter Cao.
Regarding claim 7, the combination of Segev teaches all the features with respect to claim 1 as outlined above. The combination of Segev does not explicitly teach the data storage device according to claim 1, wherein the memory controller accesses the memory device based on mapping data received from the external device, as claimed.
However, the combination of Segev in view of Cao teaches the data storage device according to claim 1, wherein the memory controller accesses the memory device based on mapping data received from the external device (Cao, [0065], the memory device 110 retrieves the one or more logical addresses and the one or more L2P entries of the L2P mapping table from the write request. The memory device 110 maps the one or more logical addresses to the one or more physical addresses based on the one or more L2P entries of the L2P mapping table; [0142], wherein the memory device is further configured to receive an L2P entry from the host device; Fig.3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Segev to incorporate teachings of Cao to receive logical to physical address mapping (L2P) from host and perform a write operation based on the L2P mapping. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Segev with Cao because it improves efficiency and performance of the storage system disclosed in Segev by avoiding delay caused by retrieving one or more L2P entries of the L2P mapping table from memory (Cao, [0027]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maroney (US2016/0370997), hereinafter Maroney in view of Yeo (US2020/0241794), hereinafter Yeo.
Regarding claim 8, Maroney teaches a memory controller (Maroney, Fig.2, controller 230) comprising:
a program control circuit (Maroney, [0050], The controller and the drive bridge may each be processing logic that includes hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.)) configured to generate a program command based on a write command that is received from an external device (Maroney, [0022], the controller 230 may receive data access requests … from a DAS interface 212 (e.g., a USB interface, a Thunderbolt interface) of the computing device 211; [0042], the disk drive 347 may support NVME commands. The controller 230 and/or drive bridge 305 may receive one or more data access requests for the disk drive 347 via the DAS interface 241. For example, the data storage device 220 may receive USB attached SCSI (UAS) commands via the DAS interfaces 241 … the NVME module 330 may translate the one or more data access requests to one or more NVME commands; Fig.2); and
a data transmission control circuit configured to receive write data from the external device (Maroney, [0022], The controller 230 may receive data access requests (e.g., data and storage access commands) from a DAS interface 212 (e.g., a USB interface, a Thunderbolt interface) of the computing device 211.) right before a start of an encoding operation for the write data associated with the program command.
Maroney does not explicitly teach receive write data from the external device right before a start of an encoding operation for the write data associated with the program command, as claimed.
However, Maroney in view of Yeo teaches receive write data from the external device right before a start of an encoding operation for the write data associated with the program command (Yeo, [0029], the write command is formatted in compliance with a vendor-specific command as defined by the NVMe protocol, which allows customized vendor-defined commands … Controller 200 processes the customized vendor-specific write command to retrieve the swap data from host memory 104, or buffer 114, and store the swap data in a location in one or more of the non-volatile memories identified by the customized vendor-defined write command).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Maroney to incorporate teachings of Yeo to have a storage controller to reformat/translate a write command into an internal program command and subsequently retrieve the corresponding write data from a host memory in order to program the write data into nonvolatile memory. A person of ordinary skill in the art would have been motivated to combine the teachings of Maroney with Yeo because it improves efficiency of the storage system disclosed in Maroney by preventing a buffer storage from being occupied by a write command for an extended period of time.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Maroney and Yeo as applied to claim 8 above, and further in view of Segev et al. (US2023/0376244), hereinafter Segev.
Regarding claim 9, the combination of Maroney teaches all the features with respect to claim 8 as outlined above. The combination of Maroney does not explicitly teach the memory controller according to claim 8, further comprising a command combination circuit configured to combine one or more write commands based on size information of the write data included with the one or more write commands, as claimed.
However, the combination of Maroney in view of Segev teaches the memory controller according to claim 8, further comprising a command combination circuit configured to combine one or more write commands based on size information of the write data included with the one or more write commands (Segev, [0045]-[0046]; [0049], The pre-aggregation module is configured to aggregate write commands for which data associated with the write commands individually do not match page size).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Maroney to incorporate teachings of Segev to aggregate write commands in order to match write data to a page size of a flash storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Maroney with Segev because it improves efficiency of the storage system disclosed in the combination of Maroney by ensuring enough buffer storage space is available in a storage controller for write commands that are ready to be executed (Segev, [0006]).
Regarding claim 10, the combination of Maroney teaches all the features with respect to claim 9 as outlined above. The combination of Maroney further teaches the memory controller according to claim 9, wherein the command combination circuit combines the one or more write commands so that the combined write command corresponds to a unit program size that is a size of data that are programmed into the memory device when the memory device performs a single program operation (Segev, [0032], The write aggregation module 208 is responsible for bringing enough data from the host device to fill at least an entire memory device page (e.g., a NAND page); [0044], A determination is made, prior to retrieving the data associated with the write command, whether the data associated with the write command will be aligned with the memory device (e.g., NAND) size at 704. If the data will be aligned, then the data is fetched at 706 and writing the data to the memory device is scheduled at 708).).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Maroney to incorporate teachings of Segev to aggregate write commands in order to match write data to a page size of a flash storage device. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Maroney with Segev because it improves efficiency of the storage system disclosed in the combination of Maroney by adaptively deciding when to fetch data and when to provide the hardware and firmware with the opportunity to classify commands before fetching the data (Segev, [0037]).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Maroney and Yeo as applied to claim 8 above, and further in view of Segev et al. (US2023/0376244), hereinafter Segev and Bai et al. (US2024/0232106), hereinafter Bai.
Regarding claim 11, the combination of Maroney teaches all the features with respect to claim 8 as outlined above. The combination of Maroney does not explicitly teach the memory controller according to claim 8, wherein the data transmission control circuit receives the write data after generating the program command when a workload is determined to be a first workload based on a command that is transmitted by the external device, as claimed.
However, the combination of Maroney in view of Segev teaches the memory controller according to claim 8, wherein the data transmission control circuit receives the write data after generating the program command when a workload is determined to be a first workload based on a command that is transmitted by the external device (Segev, [0040], A determination is made at 518 whether more data has been fetched than the required queue depth to meet performance bandwidth plus some H overhead. If FD is greater than FC+H at 518, then the mode is changed to fetch after at 520 and the controller waits for the next write command at 510. If FD is not greater than FC+H at 518, then the mode remains in fetch first and the controller waits for the next write command at 510).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Maroney to incorporate teachings of Segev to determine when to fetch corresponding write data from a host when a write command is received from a host. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Maroney with Segev because it improves efficiency of the storage system disclosed in the combination of Maroney by adaptively deciding when to fetch data and when to provide the hardware and firmware with the opportunity to classify commands before fetching the data (Segev, [0037]).
The combination of Maroney does not explicitly teach receives the write data after generating a program command, as claimed.
However, the combination of Maroney in view of Bai teaches receives the write data after generating the program command when a workload is determined to be a first workload based on a command that is transmitted by the external device (Segev, [0040]; [0049], The pre-aggregation module is configured to aggregate write commands for which data associated with the write commands individually do not match page size; Bai, [0043], in various embodiments the CDR server can produce the merged I/O request by appending expected I/O requests to an I/O request that the CDR server receives).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Maroney to incorporate teachings of Bai to append a new write command to an existing write command when the write commands need to be merged/combined. As such, fetching write data from a host is performed after a merge command is generated and fetching of write data is based on a corresponding fetch depth. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Maroney with Bai because it improves performance of the storage system disclosed in the combination of Maroney by generating a merged I/O command as soon as a last I/O command is received and appended.
Regarding claim 12, the combination of Maroney teaches all the features with respect to claim 8 as outlined above. The combination of Maroney does not explicitly teach the memory controller according to claim 8, wherein the data transmission control circuit generates the program command after receiving the write data when a workload is determined to be a second workload based on a command that is transmitted by the external device, as claimed.
However, the combination of Maroney in view of Segev teaches the memory controller according to claim 8, wherein the data transmission control circuit generates the program command after receiving the write data when a workload is determined to be a second workload based on a command that is transmitted by the external device (Segev, [0040], A determination is made at 518 whether more data has been fetched than the required queue depth to meet performance bandwidth plus some H overhead. If FD is greater than FC+H at 518, then the mode is changed to fetch after at 520 and the controller waits for the next write command at 510. If FD is not greater than FC+H at 518, then the mode remains in fetch first and the controller waits for the next write command at 510).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Maroney to incorporate teachings of Segev to determine when to fetch corresponding write data from a host when a write command is received from a host. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Maroney with Segev because it improves efficiency of the storage system disclosed in the combination of Maroney by adaptively deciding when to fetch data and when to provide the hardware and firmware with the opportunity to classify commands before fetching the data (Segev, [0037]).
The combination of Maroney does not explicitly teach generates the program command after receiving the write data, as claimed..
However, the combination of Maroney in view of Bai teaches generates the program command after receiving the write data when a workload is determined to be a second workload based on a command that is transmitted by the external device (Segev, [0040]; [0049], The pre-aggregation module is configured to aggregate write commands for which data associated with the write commands individually do not match page size; Bai, [0043], in various embodiments the CDR server can produce the merged I/O request by appending expected I/O requests to an I/O request that the CDR server receives).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Maroney to incorporate teachings of Bai to append new write command to an existing write command when the write commands need to be merged/combined. As such, fetching write data from a host is performed before a merge command is generated and fetching of write data is performed based on a corresponding fetch depth. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Maroney with Bai because it improves performance of the storage system disclosed in the combination of Maroney by generating a merged I/O command when a new I/O command is received.
Allowable Subject Matter
Claim 4, 6, 16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites “[t]he data storage device according to claim 3, wherein: the workload is determined based on a number of commands that are transmitted simultaneously by the external device and a size of the write data, and the first workload is a workload in which the number of commands that are simultaneously transmitted is greater than a set first reference value or a workload in which a product of the number of commands that are simultaneously transmitted and the size of the write data is greater than or equal to a set second reference value”.
The above-noted limitation, in combination with the other limitation of the claims, are neither disclosed nor suggested by the prior art of record. The closet prior art is Segev which teaches receiving write data based on workload, however, Segev does not teach the first workload is a workload in which the number of commands that are simultaneously transmitted is greater than a set first reference value or a workload in which a product of the number of commands that are simultaneously transmitted and the size of the write data is greater than or equal to a set second reference value. Therefore, in the context of claim 1, 3, and 4 as a whole, the prior art does not teach the claimed subject matter. Thus, the subject matter of claim 4 is allowable. Claim 16 is objected for the similar reasons.
Claim 6 recites “[t]he data storage device according to claim 1, wherein the memory controller is configured to determine a workload based on the number of commands that are simultaneously transmitted by the external device and a size of the write data, and a second workload is a workload in which a number of commands that are simultaneously transmitted is less than or equal to a set first reference value or a workload in which a product of the number of commands that are simultaneously transmitted and the size of the write data is less than a set second reference value”.
The above-noted limitation, in combination with the other limitation of the claims, are neither disclosed nor suggested by the prior art of record. The closet prior art is Segev which teaches receiving write data based on workload, however, Segev does not teach a second workload is a workload in which a number of commands that are simultaneously transmitted is less than or equal to a set first reference value or a workload in which a product of the number of commands that are simultaneously transmitted and the size of the write data is less than a set second reference value. Therefore, in the context of claim 1 and 6 as a whole, the prior art does not teach the claimed subject matter. Thus, the subject matter of claim 6 is allowable. Claim 19 is objected for the similar reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kanno et al. (2019/0179567) teaches receiving write data after a program command is generated ([0186]).
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/NANCI N WONG/Primary Examiner, Art Unit 2137
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