DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 13 February 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84(a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via the USPTO patent electronic filing system or three sets of color drawings or color photographs, as appropriate, if not submitted via the via USPTO patent electronic filing system, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification:
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
Color photographs will be accepted if the conditions for accepting color drawings and black and white photographs have been satisfied. See 37 CFR 1.84(b)(2).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2 and 13 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description and enablement requirements. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Furthermore, the claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claims 2 and 13 include the limitation “embedded multiplexer row”. The Examiner can find no examples of this phrase being used outside of this application. The specification uses this phrase in the alternative to an ICG cell, which implies that this phrase means something different from an ICG cell. The specification only explains that it may route memory input data to the memory cell row or self-feed with the old stored values. The specification fails to explain the embedded portion of the phrase. The figures do not show an embedded multiplexer row. Thus, the specification does not reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. Turning to the In re Wands factors, the claims are not overly broad and use what seems to be a specific phrase. The nature of the invention revolves around memory cell rows including an embedded multiplexer row. The prior art provides no examples of this phrase being used. The level of one of ordinary skill in the art would be a person with a master’s degree in electrical engineering or computer engineering with at least two years of experience designing memory-related circuits or mask layouts. One of ordinary skill in the art would be familiar with the general idea of a multiplexer, but not an “embedded multiplexer row”. The art is highly predictable. The inventors have provided little guidance as to the nature of this element other than stating that they “select input data” (paragraph 0057) and self-feed with the old stored values (paragraph 0039). The inventors have provided no evidence of working examples. A high degree of experimentation would be needed, since very few details have been provided. After considering all of these factors, the Examiner concludes that undue experimentation would be necessary to make or use the invention of claims 2 and 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xue et al. (US 2026/0178101) as supported by Xue et al. (CN 116959519 A) and its translation in view of Yoo et al. (US 11,289,138).
All references to Xue’s specification will include first a citation from Xue’s US PGPUB and then a citation from the translation of Xue’s Chinese application.
In regards to claims 1, 12, and 20, Xue as supported by its Chinese application and the translation of its Chinese application teaches an electronic device comprising:
a processor (“In another aspect, the present disclosure further provides a system-on-chip which may include the storage device according to any of the embodiments described above. For example, such system-on-chip may be implemented as a variety of processors, controllers, or the like.”, paragraph 0071; “The present disclosure also provides, in another aspect, a system-on-chip, which may include a storage device according to any of the foregoing embodiments. For example, such on-chip systems may be implemented as a variety of processors, controllers, and the like.”); and
a non-transitory computer readable storage medium storing instructions that, when executed, cause the processor (“In another aspect, the present disclosure further provides a system-on-chip which may include the storage device according to any of the embodiments described above. For example, such system-on-chip may be implemented as a variety of processors, controllers, or the like.”, paragraph 0071, “The present disclosure also provides, in another aspect, a system-on-chip, which may include a storage device according to any of the foregoing embodiments. For example, such on-chip systems may be implemented as a variety of processors, controllers, and the like.”) to:
receive at least a first portion of a write address bus comprising a write address from a write command at a first decoder of a memory device (“The address decoding unit 230 may be configured to perform the first address decoding on the write address to generate the enable signals en′0, . . . , en′3, which are respectively fed to the first stage of clock gating units 2440, . . . , 2443 to be combined with the input clock signal clk for generating respective enable clock signals enclk′0, . . . , enclk′3, thereby controlling whether signal flipping occurs at the clock ends CK of the respective second stage of clock gating units 2420, 2421, . . . , 24215.”, paragraph 0054, “The address decoding unit 230 may be configured to perform a first address decoding on the write address to generate enable signals en '0, ..., en' 3, which are fed into the first stage clock gating units 2440, ..., respectively.”) , wherein the memory device comprises a set of memory cells corresponding to a subset of write addresses from write commands (“Herein, for convenience of description, a latch unit corresponding to a write address may be referred to as a target latch unit, and a latch unit not corresponding to the write address may be referred to as a non-target latch unit.”, paragraph 0055, “In this context, for the convenience of description, a latch unit corresponding to a write address may be referred to as a target latch unit, and a latch unit not corresponding to a write address may be referred to as a non-target latch unit.”);
receive a first clock signal at a first primary integrated clock gating (ICG) cell of the memory device, wherein the first primary ICG cell is configured to provide a first gated clock signal to a first subcircuit of the memory device comprising a first non- empty proper subset of the memory cells, wherein the first non-empty proper subset comprises a plurality of memory cells (“For example, in FIG. 10, if it is assumed that a target latch unit is the latch unit 2200, the enable signal en′0 may be at a high level (for example, 1) so that signal flipping occurs at the respective clock ends CK of the clock gating units 2420, 2421, 2422, 2423 (the clock is turned on for one cycle), and the enable signals en′1, en′2, en′3 may be at a low level (for example, 0), so that signal flipping does not occur at the respective clock ends CK of the clock gating units 2424, 2425, . . . , 24215 (the clock is turned off).”, paragraph 0056, “For example, in FIG. 10, assuming that the target latch unit is a latch unit 2200, the enable signal en ' 0 may be at a high level (e.g., 1) so that the clock gating unit 2420, 2421, 2422, 2423, 2424, 2423, 2424, 2423, 2424, 2424, 2423, 2424, 2424, 2423, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 24 The respective clock terminal CK of 2423 performs a signal flip (one cycle of the open clock), and the enable signals en '1, en' 2, en ' 3 can be low levels (e.g., 0) so that the clock gating units 2424, 2425, ... The clock terminal CK of each of the 24215 does not have signal inversion (clock turn-off). Because the clock end CK of each clock gating unit 2424, 2425, ..., 24215 does not generate signal inversion, the enabling clock signals enclk4, enclk5, ..., The enclk15 may be at a low level (e.g., 0) such that the respective clock control terminals G of the latch units 2204, 2205, ..., 22015 do not signal flip (clock off).”; See also clock gating unit 2440 in figure 10); and
enable or disable the first primary ICG cell, when the write address is in the subset of the write addresses, based on whether the write address corresponds to any memory cell in the first non-empty proper subset of the memory cells, disabling the first primary ICG cell when the write address corresponds to a memory cell in the set of the memory cells but not in the first non-empty proper subset (“For example, in FIG. 10, if it is assumed that a target latch unit is the latch unit 2200, the enable signal en′0 may be at a high level (for example, 1) so that signal flipping occurs at the respective clock ends CK of the clock gating units 2420, 2421, 2422, 2423 (the clock is turned on for one cycle), and the enable signals en′1, en′2, en′3 may be at a low level (for example, 0), so that signal flipping does not occur at the respective clock ends CK of the clock gating units 2424, 2425, . . . , 24215 (the clock is turned off).”, paragraph 0056, “For example, in FIG. 10, assuming that the target latch unit is a latch unit 2200, the enable signal en ' 0 may be at a high level (e.g., 1) so that the clock gating unit 2420, 2421, 2422, 2423, 2424, 2423, 2424, 2423, 2424, 2424, 2423, 2424, 2424, 2423, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 2424, 24 The respective clock terminal CK of 2423 performs a signal flip (one cycle of the open clock), and the enable signals en '1, en' 2, en ' 3 can be low levels (e.g., 0) so that the clock gating units 2424, 2425, ... The clock terminal CK of each of the 24215 does not have signal inversion (clock turn-off). Because the clock end CK of each clock gating unit 2424, 2425, ..., 24215 does not generate signal inversion, the enabling clock signals enclk4, enclk5, ..., The enclk15 may be at a low level (e.g., 0) such that the respective clock control terminals G of the latch units 2204, 2205, ..., 22015 do not signal flip (clock off).”; See also clock gating unit 2440 in figure 10).
Xue as supported by its Chinese application and the translation of its Chinese application fails to teach that the memory device comprises a set of memory cell rows. Yoo teaches that the memory device comprises a set of memory cell rows (“The memory cell array 110 may include a plurality of memory cells arranged in rows and columns.”, Col. 3, lines 40-41). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Xue as supported by its Chinese application and the translation of its Chinese application with Yoo such that the memory device comprises a set of memory cell rows in order to reduce the length of the wires.
In regards to claims 2 and 13, Xue as supported by its Chinese application and the translation of its Chinese application further teaches receiving at least a second portion of the write address bus at a second decoder of the memory device (“Each clock gating unit of the second stage of clock gating units 242 is configured to receive an enable clock signal enclk′ (enclk′0, . . . , enclk′3) outputted by a respective clock gating unit of the first stage of clock gating units 244 and an enable signal en (en0, en1, . . . , en15) obtained based on second address decoding of the write address, and output an enable clock signal enclk (enclk0, enclk1, . . . , enclk15) to a respective latch unit of the latch units 2200, 2201, . . . , 22015.”, paragraph 0052, “Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”);
receiving the first gated clock signal at a first memory cell of the first non-empty proper subset in the first subcircuit (“Each clock gating unit of the second stage of clock gating units 242 is configured to receive an enable clock signal enclk′ (enclk′0, . . . , enclk′3) outputted by a respective clock gating unit of the first stage of clock gating units 244 and an enable signal en (en0, en1, . . . , en15) obtained based on second address decoding of the write address, and output an enable clock signal enclk (enclk0, enclk1, . . . , enclk15) to a respective latch unit of the latch units 2200, 2201, . . . , 22015.”, paragraph 0052, “Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”), wherein the first subcircuit further comprises an embedded multiplexer row in the first memory cell (“Respective one multiplexer unit (MUX) 11 of a plurality of multiplexer units 110, 111, . . . , 1115 (which sometimes may be collectively referred to as a multiplexer unit 11 herein) is further arranged before each latch unit 12 of the latch units 120, 121, . . . , 1215.”, paragraph 0039, “In front of each latch unit 12 in the latch units 120,121, ..., 1215, a plurality of multiplexer units (MUX) 110,111, ..., 1215 are also arranged.”); and
configuring, by the second decoder, when the write address corresponds to any memory cell in the first non-empty proper subset, the embedded multiplexer row to feed memory data input to the first memory cell or to self-feed the first memory cell with its own stored value, based on whether the write address corresponds to the first memory cell in the first non-empty proper subset of the memory cells, self-feeding the first memory cell when the write address corresponds to any memory cell in the first non-empty proper subset of the memory cells other than the first memory cell (“Each multiplexer unit 11 has a first input end for receiving write data wd and a second input end for receiving an output at an output end Q of respective one latch unit 12. Each multiplexer unit 11 has an output end coupled to an input end D of respective one latch unit 12. The storage device 10 may further include or be coupled to an address decoding unit 13 configured to perform address decoding on a write address for generating selection signals sel0, sel1, . . . , sel15, which are respectively fed to the multiplexer units 110, 111, . . . , 1115 for selecting whether to output the write data wd to the respective latch units 120, 121, . . . , 1215 or to hold original data of the latch units 120, 121, . . . , 1215.”, paragraph 0039, “The first input of each multiplexer unit 11 is used to receive the write data wd and the second input is used to receive the output at the output Q of the corresponding one latch unit 12. The output of each multiplexer unit 11 is coupled to the input D of a respective one of the latch units 12. The storage device 10 may also include or be coupled to an address decoding unit 13 configured to perform address decoding on the write address to generate select signals sel0, sel1, ..., sel15, which are fed to the multiplexer units 110, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, 111 ..., 1115 for selecting whether to output write data wd to the corresponding latch unit 120,121, ..., 1215 or to hold the original data of the latch unit 120,121, ..., 1215.”).
In regards to claims 3 and 14, Xue as supported by its Chinese application and the translation of its Chinese application further teaches receiving at least a second portion of the write address bus at a second decoder of the memory device (“Each clock gating unit of the second stage of clock gating units 242 is configured to receive an enable clock signal enclk′ (enclk′0, . . . , enclk′3) outputted by a respective clock gating unit of the first stage of clock gating units 244 and an enable signal en (en0, en1, . . . , en15) obtained based on second address decoding of the write address, and output an enable clock signal enclk (enclk0, enclk1, . . . , enclk15) to a respective latch unit of the latch units 2200, 2201, . . . , 22015.”, paragraph 0052, “Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”);
receiving the first gated clock signal at a first leaf ICG cell in the first subcircuit, wherein the first leaf ICG cell is configured to provide a first leaf gated clock signal to a first memory cell of the first non-empty proper subset of the memory cells (“Each clock gating unit of the second stage of clock gating units 242 is configured to receive an enable clock signal enclk′ (enclk′0, . . . , enclk′3) outputted by a respective clock gating unit of the first stage of clock gating units 244 and an enable signal en (en0, en1, . . . , en15) obtained based on second address decoding of the write address, and output an enable clock signal enclk (enclk0, enclk1, . . . , enclk15) to a respective latch unit of the latch units 2200, 2201, . . . , 22015.”, paragraph 0052, “Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”); and
enabling or disabling, by the second decoder, when the write address corresponds to any memory cell in the first non-empty proper subset, the first leaf ICG cell, based on whether the write address corresponds to the first memory cell in the first non-empty proper subset of the memory cells, disabling the first leaf ICG cell when the write address corresponds to any memory cell in the first non-empty proper subset of the memory cells other than the first memory cell (“In this way, although the input ends D of the latch units 220.sub.0, 220.sub.1, . . . , 220.sub.15 all receive the write data wd, the write data wd is written to only the latch unit 220.sub.0 and is not written to the latch units 220.sub.1, 220.sub.2, . . . , 220.sub.15 due to the fact that signal flipping only occurs at the clock control end G of the latch unit 220.sub.0.”, paragraph 0056, “The input terminal D of 22015 receives the write data wd, but since only the clock control terminal G of the latch unit 2200 has a signal flip, the write data wd will only be written to the latch unit 2200 and will not be written to the latch units 2201, 2202. ..., 22015.”).
In regards to claims 4 and 15, Xue as supported by its Chinese application and the translation of its Chinese application further teaches receiving at least a second portion of the write address bus at a second decoder of the memory device (“Each clock gating unit of the second stage of clock gating units 242 is configured to receive an enable clock signal enclk′ (enclk′0, . . . , enclk′3) outputted by a respective clock gating unit of the first stage of clock gating units 244 and an enable signal en (en0, en1, . . . , en15) obtained based on second address decoding of the write address, and output an enable clock signal enclk (enclk0, enclk1, . . . , enclk15) to a respective latch unit of the latch units 2200, 2201, . . . , 22015.”, paragraph 0052, “Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”);
receiving the first gated clock signal at a first secondary ICG cell in the first subcircuit of the memory device, wherein the first secondary ICG cell is configured to provide a first secondary gated clock signal to a first nested subcircuit in the first subcircuit, and wherein the first nested subcircuit comprises a first secondary non-empty subset of the first non-empty proper subset of the memory cells (“For example, FIG. 11 shows a clock gating module 240 including three stages of clock gating units (the enable signals are not shown), where the clock gating module 240 further includes a third stage of clock gating units 246 coupled between the first stage of clock gating units 244 and the second stage of clock gating units 242, which includes a plurality of clock gating units 2460, 2461, . . . , 2467.”, paragraph 0058, “For example, FIG. 11 shows a clock gating module 240 (not shown with an enable signal) including a three-stage clock gating unit, wherein the clock gating module 240 further includes a third-stage clock gating unit 246 coupled between the first-stage clock gating unit 244 and the second-stage clock gating unit 242. It includes a plurality of clock gating units 2460, 2461, ..., 2467.”); and
enabling or disabling, by the second decoder, when the write address corresponds to any memory cell in the first non-empty proper subset, the first secondary ICG cell, based on whether the write address corresponds to any memory cell in the first secondary non-empty subset of the memory cells, disabling the first secondary ICG cell when the write address corresponds to a memory cell in the first non-empty proper subset but not in the first secondary non-empty subset (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058; “Each clock gating unit in each of the one or more stages of clock gating units may be configured to receive a previous stage of clock gating unit in the one or more stages of clock gating units (near the side of the first stage clock gating unit 244). an enabling clock signal output by the corresponding clock gating unit and an enabling signal obtained by decoding based on the corresponding address of the write address, and outputting an enable clock signal to the corresponding clock gating unit in the next-stage clock gating unit (close to the side of the second-stage clock gating unit 242) of the one-stage or multi-stage clock gating unit.”).
In regards to claim 5, Xue as supported by its Chinese application and the translation of its Chinese application further teaches that the cardinality of the first non-empty proper subset of the memory cell is:
a floor of a square-root of the cardinality of the set of the memory cells; or
a ceiling of the square-root of the cardinality of the set of the memory cells (Figure 10 shows 16 latch units 220 divided into subsets of 4 latch units).
In regards to claim 6, Xue as supported by its Chinese application and the translation of its Chinese application further teaches that the first portion of the write address bus comprises upper address bits, excluding a least significant bit (LSB), of the write address bus, and the cardinality of the first non-empty proper subset of the memory cells is two to the power of the number of the remaining lower address bits of the write address bus (“In some examples, when the address is binary, if the groups obtained from grouping the latch units at the second level each include one latch unit (sixteen groups in total) and the groups obtained from grouping the latch units at the first level each include four latch units (four groups in total), the first address decoding of the write address corresponding to the first level may be associated with bits other than two lowest bits of the write address, and the second address decoding of the write address corresponding to the second level may be associated with the two lowest bits of the write address. For example, with reference to FIG. 10, if it is assumed that the latch units 2200, 2201, . . . , 22015 are respectively assigned with addresses 0000 to 1111, where an address range of the latch units 2200, 2201, 2202, 2203 is 0000 to 0011 (which belong to the same group at the first level, and each have an address with two highest bits being 00), an address range of the latch units 2204, 2205, 2206, 2207 is 0100 to 0111 (which belong to the same group at the first level, and each have an address with two highest bits being 01), an address range of the latch units 2208, 2209, 22010, 22011 is 1000 to 1011 (which belong to the same group at the first level, and each have an address with two highest bits being 10), and an address range of the latch units 22012, 22013, 2204, 22015 is 1100 to 1111 (which belong to the same group at the first level, and each have an address with two highest bits being 11).”, paragraph 0064, “In some examples, when the address is binary, if the latch units each comprise one latch unit (sixteen groups in total) in the group obtained by grouping at the second level and each comprise four latch units (four groups in total) in the group obtained by grouping at the first level, The first address decode of the write address corresponding to the first level may be associated with the remaining bits of the write address other than the lowest two bits, and the second address decode of the write address corresponding to the second level may be associated with the lowest two bits of the write address. For example, referring to FIG. 10, it is assumed that latch units 2200, 2201, ..., 22015 are assigned addresses 0000 to 1111, respectively, wherein latch units 2200, 2201, 2202, ..., 22015 are assigned addresses, respectively. 2203 the address range is 0000 to 0011 (they belong to the same group at the first level, the highest two bits of the address are 00), latch unit 2204, 2205, 2206, The address range of 2207 is 0100 to 0111 (they belong to the same group at the first level, the highest two bits of the address are 01), latch unit 2208, 2209, 22010, The address range of 22011 is 1000 to 1011 (they belong to the same group at the first level, the highest two bits of the address are 10), the latch unit 22012, 22013, 2204, The address range of 22015 is 1100 to 1111 (they belong to the same group at the first level, and the highest two bits of the address are both 11).”).
In regards to claim 7, Xue as supported by its Chinese application and the translation of its Chinese application further teaches that the number of the remaining lower address bits is a floor or a ceiling of one-half of a size of the write address bus (“In some examples, when the address is binary, if the groups obtained from grouping the latch units at the second level each include one latch unit (sixteen groups in total) and the groups obtained from grouping the latch units at the first level each include four latch units (four groups in total), the first address decoding of the write address corresponding to the first level may be associated with bits other than two lowest bits of the write address, and the second address decoding of the write address corresponding to the second level may be associated with the two lowest bits of the write address. For example, with reference to FIG. 10, if it is assumed that the latch units 2200, 2201, . . . , 22015 are respectively assigned with addresses 0000 to 1111, where an address range of the latch units 2200, 2201, 2202, 2203 is 0000 to 0011 (which belong to the same group at the first level, and each have an address with two highest bits being 00), an address range of the latch units 2204, 2205, 2206, 2207 is 0100 to 0111 (which belong to the same group at the first level, and each have an address with two highest bits being 01), an address range of the latch units 2208, 2209, 22010, 22011 is 1000 to 1011 (which belong to the same group at the first level, and each have an address with two highest bits being 10), and an address range of the latch units 22012, 22013, 2204, 22015 is 1100 to 1111 (which belong to the same group at the first level, and each have an address with two highest bits being 11).”, paragraph 0064, “In some examples, when the address is binary, if the latch units each comprise one latch unit (sixteen groups in total) in the group obtained by grouping at the second level and each comprise four latch units (four groups in total) in the group obtained by grouping at the first level, The first address decode of the write address corresponding to the first level may be associated with the remaining bits of the write address other than the lowest two bits, and the second address decode of the write address corresponding to the second level may be associated with the lowest two bits of the write address. For example, referring to FIG. 10, it is assumed that latch units 2200, 2201, ..., 22015 are assigned addresses 0000 to 1111, respectively, wherein latch units 2200, 2201, 2202, ..., 22015 are assigned addresses, respectively. 2203 the address range is 0000 to 0011 (they belong to the same group at the first level, the highest two bits of the address are 00), latch unit 2204, 2205, 2206, The address range of 2207 is 0100 to 0111 (they belong to the same group at the first level, the highest two bits of the address are 01), latch unit 2208, 2209, 22010, The address range of 22011 is 1000 to 1011 (they belong to the same group at the first level, the highest two bits of the address are 10), the latch unit 22012, 22013, 2204, The address range of 22015 is 1100 to 1111 (they belong to the same group at the first level, and the highest two bits of the address are both 11).”).
In regards to claims 9 and 17, Xue as supported by its Chinese application and the translation of its Chinese application further teaches receiving the first clock signal at a second primary ICG cell of the memory device, wherein the second primary ICG cell is configured to provide a second gated clock signal to a second subcircuit of the memory device comprising a second non-empty subset of the memory cells that is disjoint with the first non-empty proper subset (“the clock gating unit 2441 is coupled to the clock gating units 2424, 2425, 2426, 2427 and is thus coupled to the latch units 2204, 2205, 2206, 2207”, paragraph 0053, “the clock gating unit 2442 and the clock gating unit 2428, 2429, 24210, 24211 are further coupled with the latch unit 2208, 2209, 22010”); and
enabling or disabling, by the first decoder, when the write address is in the subset of the write addresses, the second primary ICG cell, based on whether the write address corresponds to any memory cell in the second non-empty subset of the memory cells, disabling the second primary ICG cell when the write address corresponds to a memory cell in the set of the memory cells but not in the second non-empty subset (“an address range of the latch units 220.sub.4, 220.sub.5, 220.sub.6, 220.sub.7 is 0100 to 0111 (which belong to the same group at the first level, and each have an address with two highest bits being 01)”, paragraph 0064, “latch unit 2204, 2205, 2206, The address range of 2207 is 0100 to 0111 (they belong to the same group at the first level, the highest two bits of the address are 01)”).
In regards to claims 10 and 18, Xue as supported by its Chinese application and the translation of its Chinese application further teaches that the second portion of the write address bus is non-overlapping with the first portion of the write address bus (“the groups obtained from grouping the latch units at the first level each include four latch units (four groups in total), the first address decoding of the write address corresponding to the first level may be associated with bits other than two lowest bits of the write address”, paragraph 0064, “the group obtained by grouping at the second level and each comprise four latch units (four groups in total) in the group obtained by grouping at the first level, The first address decode of the write address corresponding to the first level may be associated with the remaining bits of the write address other than the lowest two bits, and the second address decode of the write address corresponding to the second level may be associated with the lowest two bits of the write address.”), further comprising:
receiving the first clock signal at a second primary ICG cell of the memory device (clock gating unit 2443, figure 11), wherein the second primary ICG cell is configured to provide a second gated clock signal (enclk’3, figure 11) to a second subcircuit of the memory device comprising a second non-empty subset of the memory cells that is disjoint with the first non-empty proper subset ( latch units 22012-22016);
enabling or disabling, by the first decoder, when the write address is in the subset of the write addresses, the second primary ICG cell, based on whether the write address corresponds to any memory cell in the second non-empty subset of the memory cells (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058; “Each clock gating unit in each of the one or more stages of clock gating units may be configured to receive a previous stage of clock gating unit in the one or more stages of clock gating units (near the side of the first stage clock gating unit 244). an enabling clock signal output by the corresponding clock gating unit and an enabling signal obtained by decoding based on the corresponding address of the write address, and outputting an enable clock signal to the corresponding clock gating unit in the next-stage clock gating unit (close to the side of the second-stage clock gating unit 242) of the one-stage or multi-stage clock gating unit.”),
disabling the second primary ICG cell when the write address corresponds to a memory cell in the set of the memory cells but not in the second non-empty subset (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058; “Each clock gating unit in each of the one or more stages of clock gating units may be configured to receive a previous stage of clock gating unit in the one or more stages of clock gating units (near the side of the first stage clock gating unit 244). an enabling clock signal output by the corresponding clock gating unit and an enabling signal obtained by decoding based on the corresponding address of the write address, and outputting an enable clock signal to the corresponding clock gating unit in the next-stage clock gating unit (close to the side of the second-stage clock gating unit 242) of the one-stage or multi-stage clock gating unit.”);
receiving the second gated clock signal (enclk’3, figure 11) at a second secondary ICG cell (clock gating unit 2466, figure 11) in the second subcircuit of the memory device, wherein the second secondary ICG cell is configured to provide a second secondary gated clock signal (enclk’’6, figure 11) to a second nested subcircuit in the second subcircuit, and wherein the second nested subcircuit comprises a second secondary non-empty subset of the second non-empty subset of the memory cells (latch units 22012 and 22013, figure 11); and
enabling or disabling, by the second decoder, when the write address corresponds to any memory cell in the second non-empty subset, the second secondary ICG cell, based on whether the write address corresponds to any memory cell in the second secondary non-empty subset of the memory cells, disabling the second secondary ICG cell when the write address corresponds to a memory cell in the second non-empty subset but not in the second secondary non-empty subset (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058; “Each clock gating unit in each of the one or more stages of clock gating units may be configured to receive a previous stage of clock gating unit in the one or more stages of clock gating units (near the side of the first stage clock gating unit 244). an enabling clock signal output by the corresponding clock gating unit and an enabling signal obtained by decoding based on the corresponding address of the write address, and outputting an enable clock signal to the corresponding clock gating unit in the next-stage clock gating unit (close to the side of the second-stage clock gating unit 242) of the one-stage or multi-stage clock gating unit.”).
In regards to claims 11 and 19, Xue as supported by its Chinese application and the translation of its Chinese application further teaches receiving at least a third portion of the write address bus at a third decoder of the memory device (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058, “Each clock gating unit in the first stage clock gating unit 244 is configured to receive an input clock signal clk and an enable signal en '(en' 0, ......, n) decoded based on the first address of the write address. and en '3), and outputs an enable clock signal enclk' (enclk '0, ..., enclk' 3) to the corresponding clock gating unit in the second stage clock gating unit 242. Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”);
receiving the first secondary gated clock signal at a first tertiary ICG cell in the first nested subcircuit of the memory device, wherein the first tertiary ICG cell is configured to provide a first tertiary gated clock signal to a first double-nested subcircuit in the first nested subcircuit, and wherein the first double-nested subcircuit comprises a first tertiary non-empty subset of the first secondary non-empty subset of the memory cell rows (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058, “Each clock gating unit in the first stage clock gating unit 244 is configured to receive an input clock signal clk and an enable signal en '(en' 0, ......, n) decoded based on the first address of the write address. and en '3), and outputs an enable clock signal enclk' (enclk '0, ..., enclk' 3) to the corresponding clock gating unit in the second stage clock gating unit 242. Each clock gating unit in the second stage clock gating unit 242 is configured to receive an enable clock signal enclk '(enclk' 0, ..., ...,) output by a corresponding clock gating unit in the first stage clock gating unit 244. Enclk ' 3) and an enable signal en (en0, en1, ..., en15) obtained based on the second address decoding of the write address, and to latch units 2200, 2201, ..., The corresponding latch unit in 22015 outputs an enable clock signal enclk (enclk0, enclk1, ..., enclk15).”); and
enabling or disabling, by the third decoder, when the write address corresponds to any memory cell row in the first secondary non-empty subset, the first tertiary ICG cell, based on whether the write address corresponds to any memory cell row in the first tertiary non-empty subset of the memory cell rows, disabling the first tertiary ICG cell when the write address corresponds to a memory cell row in the first secondary non-empty subset but not in the first tertiary non-empty subset (“Each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units may be configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units (at a side close to the first stage of clock gating units 244) of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address, and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units (at a side close to the second stage of clock gating units 242) of the one or more stages of clock gating units.”, paragraph 0058; “Each clock gating unit in each of the one or more stages of clock gating units may be configured to receive a previous stage of clock gating unit in the one or more stages of clock gating units (near the side of the first stage clock gating unit 244). an enabling clock signal output by the corresponding clock gating unit and an enabling signal obtained by decoding based on the corresponding address of the write address, and outputting an enable clock signal to the corresponding clock gating unit in the next-stage clock gating unit (close to the side of the second-stage clock gating unit 242) of the one-stage or multi-stage clock gating unit.”).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xue et al. (US 2026/0178101) as supported by Xue et al. (CN 116959519 A) and its translation in view of Yoo et al. (US 11,289,138) and Casarsa (US 2023/0343405).
In regards to claims 8 and 16, Yoo further teaches disabling the first primary ICG cell when the write enable signal is de-asserted (“Referring to FIGS. 4 and 5, as the write enable signal En_W is transited from a first time point t1 to a first phase (for example, logic high), the clock Clk may be output to the first shared latch SL1, the second shared latch SL2, and the first latch L1 to the third latch L3.”, Col. 6, lines 11-16).
Xue as supported by its Chinese application and the translation of its Chinese application in view of Yoo fails to teach receiving a write enable signal at the first decoder. Casarsa teaches receiving a write enable signal at the first decoder (“With 121 is indicated thus a one hot address decoder, e.g., which outputs decoded signals in the form of sequence of bits with only one logic one, receiving the address signal SAB and sampled write enable SWE and outputting one hot decoded address signals DAB0 . . . DABW to respective integrated clock gating cells 1230 . . . 123W, which output a respective gated clock signals GC0 . . . GCW.”, paragraph 0051) “to enable writing in the single port RAM” (paragraph 0038). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Xue as supported by its Chinese application and the translation of its Chinese application with Yoo and Casarsa to include receiving a write enable signal at the first decoder “to enable writing in the single port RAM” (id.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kaburlasos (US 2007/0156995) teaches RAM clock gating of banks. Vilangudipitchai (US 8,848,429) teaches clock gating master and slave latches. Botea (US 2016/0093400) teaches clock gating memory banks. Rouge (US 2018/0275193) teaches clock gating based on rows and columns. Kalla (US 2019/0019547) teaches clock gating memory core circuits. Gu (US 2021/0390383) teaches clock gating all but one bank based on an address. Irfan (US 2021/0398591) teaches clock gating memory banks based on an address. Jain (US 2023/0170010) teaches clock gating a bank array of memory partitions. Li (US 2023/0223054) teaches clock gating a latch array. Kim (KR 10-2017-0034210) as supported by its translation teaches clock gating different blocks. Tang (CN 111753962) as supported by its translation teaches addressing memory blocks by bits and clock gating. Hong et al. ("Design and Implementation of 32-bit SDRAM Memory Controller with Optimized Dynamic Power using ASIC") teaches multistage clock gating.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 30 July 2026
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