Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 03/03/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 12 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over ALAMELDEEN et al. (US Pub. 2019/0041952) in view of Batcher (Patent No.: US 7,010,579).
Regarding claim 10, ALAMELDEEN discloses a memory processing method comprising:
configuring data flow (Fig.3: first communication path 320) between compute cores of one or more of a plurality of processing regions (Fig.3: Host cores 30) and corresponding adjacent ones of a plurality of regions of a first memory (Fig.3: NMP complex 306), wherein the plurality of processing regions (Fig.3: Host cores 30) are interleaved between the plurality of regions (Fig.3: Memory 308) of the first memory (Fig.3: NMP complex 306); configuring data flow between the compute cores within respective ones of the one or more of the plurality of processing regions (Fig.3 and [0022]-[0026]: a first communication path 320 is used to transfer data between the host cores 304 and the NMP complex 306. A second communication path 322 is used to transfer data between the memory 308 and the PIM cores 310. The second communication path 322 is of a higher bandwidth in terms of rate of data transfer in comparison the first communication path 320. The second communication path 322 may be referred to as a high bandwidth path and the first communication path 320 may be referred to as a low bandwidth path. The first communication path 320 is of a lower bandwidth is comparison to the second communication path 322 as the physical distance between the host cores 304 and the NMP complex 306 is greater than the physical distance between the memory 308 and the PIM cores 310 within the NMP complex 306).
However, ALAMELDEEN does not specifically teach synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data.
Batcher teaches synchronizing data movement between one or more compute cores (Fig.3: PHY Processing System 5) producing given data and one or more other compute cores (Fig.3: Host Processor 60) consuming the given data (col.4, lines 1-9: Consequently, data arrives at a non-uniform data rate and thus requires a FIFO memory to synchronize the data traffic between PHY data processing system 5 and HOST processor 60. Therefore, the PHY data processing system, MAC processor 30 and HOST processor 60 operate independently of each other to form a loosely coupled system, which requires FIFOs for coordination and synchronization).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate synchronizing the data traffic , as taught by Batcher into the Near-Memory Processing (NMP) mechanism of ALAMELDEEN, in order to overcomes the slow data transfer rates of prior art data transfer systems to provide a data transfer system that provides the necessary throughput required by the higher data processing rates.
Regarding claim 12, ALAMELDEEN teaches configuring data flow between a second memory and the compute cores of one or more of the plurality of processing regions (Fig.3 and Fig.4).
Regarding claim 15, ALAMELDEEN teaches configuring one or more input/output stages to stream data into a first one of the plurality of regions of the first memory and stream data out from a last one of the plurality of regions of the first memory (Fig.3 and [0022]-[0026]).
Regarding claim 16, ALAMELDEEN teaches configuring the compute cores in one or more of the plurality of processing regions in one or more clusters (Fig.3 and [0022]-[0026]).
Regarding claim 17, ALAMELDEEN teaches configuring two or more of the compute cores in one or more of the plurality of processing regions to be communicatively coupled in series (Fig.3 and [0022]-[0026]).
Regarding claim 18, ALAMELDEEN teaches configuring a plurality of physical channels of one or more of the compute cores of one or more of the plurality of processing regions (Fig.3 and [0022]-[0026]).
Regarding claim 19, ALAMELDEEN teaches configuring a plurality of virtual channels of one or more of the compute cores of one or more of the plurality of processing regions (Fig.3 and [0022]-[0026]).
Allowable Subject Matter
Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 13 identifies the distinct features “configuring one or more sets of the compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model; loading weights for the neural network model into the second memory; loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model", which are not taught or suggested by the prior art of records.
Claim 14 identifies the distinct features “wherein configuring the data flow of the compute cores of the plurality of processing regions, the plurality of regions of the first memory and the second memory comprises one of a whole channel compute core configuration, a partial sum compute core configuration, a polymorphic first memory compute core configuration, a polymorphic second memory compute core configuration and a compound compute core configuration", which are not taught or suggested by the prior art of records.
Claims 13 and 14 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Reasons of Allowance
Claims 1-10 are allowed.
The closest prior art, ALAMELDEEN et al. (US Pub. 2019/0041952), discloses “configuring data flow between compute cores of one or more of a plurality of processing regions and corresponding adjacent ones of a plurality of regions of a first memory; configuring data flow between a second memory and the compute cores of the one or more of the plurality of processing regions; configuring data flow between the compute cores within respective ones of the one or more of the plurality of processing regions”.
However, the prior art differs from the present invention because the prior art fails to disclose “configuring one or more sets of the compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model; loading weights for the neural network model into the second memory; loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model”.
The following is an examiner’s statement of reasons for allowance:
Independent Claim 1 identifies the distinct features “configuring one or more sets of the compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model; loading weights for the neural network model into the second memory; loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model", which are not taught or suggested by the prior art of records.
Claims 1-10 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records. The above features in conjunction with all other limitations of the dependent and independent claims 1-10 are hereby allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cherukuri et al. (Pub. No.: US 2014/0006714) “SCALABLE COHERENCE FOR MULTI-CORE PROCESSOR”
Considered for teachings related to multi-core processors. In particular, embodiments relate to maintaining data coherence in multi-core processors.
Does not disclose or suggest configuring one or more sets of the compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model; loading weights for the neural network model into the second memory; loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model.
PELLEY, III et al. (Pub. No.: US 2011/0093660) “MULTI-CORE PROCESSING SYSTEM”
Considered for teachings related to processing systems, and more specifically, to processing systems having a plurality of cores.
Does not disclose or suggest configuring one or more sets of the compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model; loading weights for the neural network model into the second memory; loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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