DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 3-7-2025 have been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (USPAP 2021/0166774) in view of Liikanen (USPAP 2020/0185034).
Claims 1, 8 and 15:
Cha substantially teaches the claimed invention. Cha teaches a memory device or storage system comprising a non-volatile memory (NVM) (120) coupled to a controller (110) (“control logic”) that may output a command (CMD), an address (ADDR) and control signals (CTRL) to the NVM (see fig. 1, and par. 0035). Cha teaches that the controller receives a read request from host 200 and controls the overall operations of the storge device (see par. 0038). Cha teaches that the NVM may comprises one or more memory blocks (BLK) which are grouped into a plurality of super blocks (SB) and the super blocks may include a plurality of memory cells such as single-level cells (SLCs) or multi-level cells (MLCs) or quad-level cells (QLCs) as well as each of the memory cells may store one or more bits of data such as data blocks (see par. 0036). Cha teaches that the blocks may include a plurality of pages wherein memory cells connected to a same word-line may constitute a page and a block is a unit of erase operation and a page a unit of program operation (see par. 0037 to 0038).
Cha teaches that the controller reads data DATA stored in the NVM based on a read request received from the host and performs operations on super blocks that comprises a plurality of blocks grouped based on threshold voltage distribution characteristics of the plurality of blocks (see par. 0040). Cha teaches that the controller performs a read operation on the first memory block of a first supper block based on a first read level (see par. 0046). Cha teaches that the controller includes a history buffer (HB) that stores the read levels and to compensate for differences in characteristics between a plurality of blocks included in the same supper block, the controller adds an offset to the history ready level to generate an adjusted history read level (see par. 0050).
Cha teaches that by adding an offset to the read level, the read level is adjusted and inturn increases the read success rate (see par. 0052). Cha teaches that when a read operation is performed on the memory cells using the first default read level to the third default read level (DRL1 to DRL3), a read error may occur in some of the memory cells and to correct the read error an error correction code maybe used (see par. 0078).
Cha fails to teach that the storage system comprises the limitation of: “a respective read window corresponding to a respective valley margin between a respective pair of adjacent threshold voltage distribution;” however, Liikanen in an analogous art teaches a memory subsystem comprising a controller (108) coupled to a memory component (110) having various combination of different types of memory components wherein the controller receives a read request from a host (102) (see fig. 1 and par. 0024). Liikanen teaches that programming the memory cells includes a reading window that can be referred to as a distance in voltage between adjacent threshold voltage (Vt) distributions at a particular bit error rate (see par. 0017). Liikanen further teaches that a reading window may also be referred as a valley margin, since the Vt distributions include respective peaks with the regions therebetween being referred to as valleys (see par. 0017). Liikanen teaches that the reading window (436) can be a distance between adjacent edges of the Vt distributions (440-1, 440-2) (see par. 0036).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the storage system of Cha to include the reading window for adjacent edges of Liikanen because Liikanen teaches that a reading window budget (RWB) corresponding to a particular group of memory cells supports managing and maintaining system characteristics such as QoS or error rate. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ in a storage system an element such as a reading window budget for adjacent edges to aid in managing system characteristics such as QoS or error rate as taught by Liikanen (see par. 0017).
As to the further limitation of the claim, Cha teaches that a changed distribution may be a distribution obtained after a predetermined time since the program operation on the memory cells has completed. Cha also teaches that when a retention time (elapsed time) increases, the amount of charges trapped in the memory cells may be reduced (see par. 0077).
As per claims 2, 9 and 16, Cha teaches grouping a plurality of physical blocks of NVM into a plurality of groups based on characteristic information about each of the plurality of physical blocks (see par. 0008). Cha teaches that the NVM may comprises one or more memory blocks (BLK) which are grouped into a plurality of super blocks (SB) (see par. 0036).
As per claims 3, 10 and 17, Cha teaches that the plurality of blocks of the NVM may be grouped into a plurality of super blocks on various conditions (see fig. 3A & 3B and, par. 0069), Cha teaches that a method for regrouping super groups of the storage device comprises computing a characteristic value and regrouping the supper blocks based on the computed characteristic value (see fig. 18 and par. 0160 et seq.).
As per claims 4 to 5, 11 to 12 and 18 to 19, Cha teaches that the controller may add an offset to the read level of the history buffer, calculate an adjusted read level, and perform the history read operation based on the adjusted read level (see par. 0050). Cha teaches that based on the revised read levels (CRL1a, CRL2a, and CRL3a) the controller may ascertain which block the read level is obtained from block (B21) and based on an offset in which differences in electrical characteristics between the block (B21) and a block on which a history read operation is to be performed are reflected, and perform the history read operation based on the adjusted read levels (see par. 0090).
As per claims 6, 13 and 20, Cha teaches that the threshold-voltage distribution characteristics such as a width of a threshold voltage distribution of the first block may be different from those of the second block (see par. 0108 et seq.).
As per claims 7 and 14, Cha teaches that the plurality of blocks may be grouped into a plurality of super blocks (i.e., first to k-th supper blocks) based on electrical characteristics and may be grouped into super blocks based on various conditions (see par. 0068 to 0069). Cha teaches that the characteristic value may include a width of a threshold voltage distribution and a minimum level of a threshold voltage (see par. 0160).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. USPAP 2019/0348133) discloses a method and an apparatus for adapting a read reference voltage to be used in reading flash memory based one or more channel conditions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
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