The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: READ-MODIFY-WRITE MANAGER WITH PIPELINED ARITHMETIC CIRCUIT AND POINTER BASED UPDATE QUEUE.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 9, 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims are directed to one or more device/method.
The claimed invention, when taken as a whole, is directed to the abstract idea of performing an arithmetic operation on the first value and the first read value to produce a first result, corresponding to performing a mental/math process as shown below (2A Prong 1 elements are bolded and 2A prong 2 and 2B elements are italicized). These are data collection, measurement, and analysis steps that result in determining/identifying results of analysis which fall within the categories of abstract ideas identified as a mental process and/or math, which is an abstract idea under step 2a prong I.
In the following claim, 2A Prong 1 elements are bolded and 2A prong 2 and 2B elements are italicized.
Claim 1 recites: 1. A device comprising: a first memory; a second memory; an arithmetic pipeline coupled to the first memory; a write pipeline coupled to the arithmetic pipeline; and a controller coupled to the arithmetic pipeline and the write pipeline, wherein: the first memory is configured to: receive a first value and a first indicator of a memory location of the second memory; store the first value and the first indicator; receive a first read value associated with the memory location; and store the first read value; the arithmetic pipeline is configured to perform an arithmetic operation on the first value and the first read value to produce a first result; and the write pipeline is configured to store the first result in the second memory.
Under step 2A prong 2 of the 101 analysis: The claims do not recite any specific improvements to the functioning of the computer or memory hardware itself. The memory, write/arithmetic pipeline, controller, & first memory are described in generic terms and operate in their ordinary capacities to store & move data. The receiving, storing, receiving, storing, and the last storing limitations are additional elements that do not integrate the invention into a practical application because they are insignificant extra-solution activity. These particular elements form high level decision logic that do not integrate the abstract idea into a practical application in the manner of an improvement to computer functionality and are simply conduits for performing the abstract idea of data collection and analysis. Under step 2B of the 101 analysis the claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they are treated as insignificant extra-solution activity or as merely implementing the abstract idea (apply it) using generic computer components and these are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)(II). As such, the claims do not amount to significantly more than the abstract idea.
The additional elements in the dependent claims 2-8, 10-17, 19-20 are similarly rejected because they function to link the abstract idea to the performance of further arithmetic/pointer-increment/forwarding operations resulting in data collection/analysis/storing using pipelines/memory, circular buffers etc, and do not integrate the abstract idea into a practical application. Such generic computer implementation does not impose a meaningful limit on practicing the abstract idea & implementing an abstract idea on a generic computer does not integrate the abstract idea into a practical application.
In conclusion, the claims do not recite a transformation of an article, nor do they add any meaningful limitations beyond generally linking the abstract idea to a technological environment of a generic memory system/device. Thus the abstract idea is not integrated into a practical application and the claims do not include additional elements individually or in combination that amount to significantly more than the abstract idea itself.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-9, 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bhoria et al (US PGPUB # 20230401162) in view of Cho et al (US PGPUB # 20050198458). With respect to independent claim 1, 9, 18 Bhoria/Cho discloses: A device comprising:
a first memory [L1 cache, store queue, victim store queue – Bhoria fig 1-2];
a second memory [main storage and/or victim storage - Bhoria fig 1-2];
an arithmetic pipeline coupled to the first memory [arithmetic pipeline/component, RMW merge, ECC components – Bhoria fig 4a, paragraph 0112];
a write pipeline coupled to the arithmetic pipeline [r/w merge 408 - Bhoria fig 4a, paragraph 0112-0113]; and
a controller coupled to the arithmetic pipeline and the write pipeline [controllers 220, 222, 414 and arbitration manager - Bhoria fig 4a, paragraph 0112-0113], wherein:
the first memory is configured to: receive a first value and a first indicator of a memory location of the second memory [store instructions 1018, 1020, 1022 include example data, such as WDATA, ADDR, BYTEN, SIZE, and R/W. WDATA corresponds to data (e.g., 64 bits of data) to be written and/or otherwise stored in at least one of the main cache store queue 212 or the main storage 214. ADDR corresponds to a data address associated with at least one of the main cache store queue 212 or the main storage 214. BYTEN corresponds to byte enable data. SIZE corresponds to a data size of a data access operation (e.g., a read operation, a write operation, a modify operation, etc., and/or a combination thereof). R/W corresponds to whether the store instruction is a read operation or a write operation – Bhoria 0568; write/store instruction includes data WDATA and address which goes to main cache store queue 212 via write port & signals/data/command paths including MS/STQ_ADDR - Bhoria fig 10a1-a2];
store the first value and the first indicator [latches 402a, 402b, 402c, 402d, 402e, are electronic devices configured to store information (e.g., bytes, bits, etc.) obtained by the main cache store queue 212. The example latches 402a-c pass the write data and information corresponding to whether the write data needs to be combined with the read and corrected data out of the ECC logic 310 in the arithmetic unit 404, the atomic unit 406, and/or the RMW merge component 408. In the example of FIG. 4A, the latch 402a is communicatively coupled to the cache controller 220 to obtain read, write, and/or modify instructions. Such read, modify, and/or write instructions may originate from the CPU 102, and transmitted to the latch 402a via the cache controller 220. Latch 402a is coupled to latch 402b, the tag RAM 208, the arbitration manager 414, and the pending store address data store 416 to transmit such read, modify, and/or write instructions to the latch 402b, the tag RAM 208, the arbitration manager 414, and the pending store address data store 416 - Bhoria fig 4a, paragraph 0112-0113; write/store instruction includes data WDATA and address which goes to main cache store queue 212 via write port & signals/data/command paths including MS/STQ_ADDR - Bhoria fig 10a1-a2];
receive a first read value associated with the memory location [value obtained from the read, modify, and/or write instruction (e.g., the byte value, the bit value, etc.), propagates through the main cache store queue 212 -Bhoria 0114; during RMW operation arbitration manager 414 issues read to main storage, read data and its ECC are provided to ECC logic 310, corrected and then sent to RMW pipeline including latches 402c-d, wherein the pipeline latches 402a-e are described as part of main cache store queue and hold values associated with pending write/store operations - Bhoria 0121, 0124 fig 4a path from 214 [Wingdings font/0xE0] 310 [Wingdings font/0xE0] 402c-d & 408]; and
store the first read value [latches buffer/store values corresponding to r/w requests as they pass through the system between functional components Bhoria 0112-0115; during RMW operation arbitration manager 414 issues read to main storage, read data and its ECC are provided to ECC logic 310, corrected and then sent to RMW pipeline including latches 402c-d, wherein the pipeline latches 402a-e are described as part of main cache store queue and hold values associated with pending write/store operations until arithmetic/RMW merge completes- Bhoria 0121, 0124 fig 4a] [input buffer stores a read data signal received from the memory and the stored read data is later provided to the data modification unit – Cho 0022, 0027 claims 1-3, fig 2-3];
the arithmetic pipeline is configured to perform an arithmetic operation on the first value and the first read value to produce a first result [Arithmetic component performs arithmetic operations on data from main storage and stores queue values in a RMW context, so that together with RMW merge component, arithmetic unit updates the stored word using new data from the store queue and existing data from memory - Bhoria 0115, 0118-0119, fig 4a] [Data modification unit performs an arithmetic operation on the read data signal (first read value) and an arithmetic data signal (first value) and outputs the result of the arithmetic operation as a modified data signal to produce a result – Cho claims 1-3]; and
the write pipeline is configured to store the first result in the second memory [After RMW merge & ECC merged data and ECC bits are sent to arbitration manager, the updated word is written back into main storage or victim storage, this is a write pipeline that stores the result in the second memory - Bhoria 0115, 0118-0119, fig 4a] [Modify data signal from data modification unit is selected by selection unit and stored in output buffer and then written to memory as modified data – Cho fig 3, claims 1-3].
Bhoria does not explicitly disclose a first memory storing a first value and a first indicator in addition to a first red value & an arithmetic pipeline configured to perform an arithmetic operation on the first value and the first read value to produce a first result, although Bhoria appears to at least suggest these limitations as indicated above. Nevertheless in the same field of endeavor Cho teaches a memory controller having a RMW function that operates as a first memory storing a first value and a first indicator in addition to a first red value & an arithmetic pipeline configured to perform an arithmetic operation on the first value and the first read value to produce a first result – Cho abstract, fig 3, paragraph 0023-0024, claims 1-3.
Therefore, Bhoria/Cho teaches all limitations of the instant claim(s).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a first memory storing a first value and a first indicator in addition to a first red value & an arithmetic pipeline configured to perform an arithmetic operation on the first value and the first read value to produce a first result in the invention of Bhoria as taught by Cho because it would be advantageous for reducing an occupation time for the system bus and an access time for the memory (Cho abstract).
With respect to dependent claims 6, 15 Bhoria/Cho discloses a data forwarding block [write data forwarding – Bhoria fig 3c, 4b]; wherein the first memory, the arithmetic pipeline, and the write pipeline are configured to provide indicators to the data forwarding block [Bhoria fig 4b, 11b1-2]; wherein the data forwarding block is configured to compare an indicator provided from a memory location of the first memory to the indicator provided from the arithmetic pipeline or the write pipeline to determine whether there is a matching indicator [Bhoria fig 4b, 11b1-2]; wherein the data forwarding block is configured to, responsive to the matching indicator, provide a read value or result corresponding to the matching indicator to the first memory [Bhoria fig 4b, 11b1-2]; and wherein the first memory is configured to store the corresponding read value or corresponding result in the memory location of the first memory [Bhoria fig 4b, 11b1-2].
With respect to dependent claims 7, 16 Bhoria/Cho discloses wherein the controller is configured to invalidate a write transaction corresponding to the matching indicator [If the comparator(s) 420 determine that any two or more write instructions output by the latches 402b-d corresponds to the same memory address (block 1506: YES), control continues to block 1508. For each group of write instructions corresponding to the same memory address (blocks 1508-1514), the one or more of the example merging circuit 1103a-c that receive(s) write instructions for the same memory address maintain(s) the write data for the byte(s) for the newest write instructions (e.g., the write instructions that were more recently received from the CPU 102) that overlap the write data for the same byte(s) from older write instructions (block 1510) – Bhoria 0755].
With respect to dependent claims 8, 17 Bhoria/Cho discloses wherein the first memory is configured to be circularly addressed [the queues disclosed in Bhoria are understood to be circularly addressed. The examiner is taking official notice that addressing a memory in a circular manner would have been obvious to one of ordinary skill in the art before the effective filing date of the invention because it would be advantageous for reducing read latency and improving SSD speed (Halaharivi 0004) as evidenced by the abstract of Halaharivi et al (US PGPUB # 20160291868)].
Claims 2, 10, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bhoria/Cho in view of Halaharivi et al (US PGPUB # 20160291868).
With respect to dependent claims 2, 10, 19 Bhoria/Cho does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Halaharivi teaches out of order SGL read sorting using three pointers into a first memory (circular buffer) such that the combination of Bhoria/Cho/Halaharivi discloses wherein the controller is configured to maintain a first pointer indicating a first memory location of the first memory [controller maintains multiple pointers indicating memory locations in first memory – Bhoria fig 24-29, paragraph 0487-0488] [queue is a circular buffer having a write pointer, a read pointer, and a special read pointer associated therewith, the write pointer being advanced each time contents are written into the buffer, the read pointer being advanced when oldest valid contents in the buffer are read, and the special read pointer being advanced when valid contents in the buffer, excluding the oldest valid contents, are read – Halaharivi abstract], a second pointer indicating a second memory location of the first memory [controller maintains multiple pointers indicating memory locations in first memory – Bhoria fig 24-29, paragraph 0487-0488] [queue is a circular buffer having a write pointer, a read pointer, and a special read pointer associated therewith, the write pointer being advanced each time contents are written into the buffer, the read pointer being advanced when oldest valid contents in the buffer are read, and the special read pointer being advanced when valid contents in the buffer, excluding the oldest valid contents, are read – Halaharivi abstract], and a third pointer indicating a third memory location of the first memory [queue is a circular buffer having a write pointer, a read pointer, and a special read pointer associated therewith, the write pointer being advanced each time contents are written into the buffer, the read pointer being advanced when oldest valid contents in the buffer are read, and the special read pointer being advanced when valid contents in the buffer, excluding the oldest valid contents, are read – Halaharivi abstract]; wherein the first memory is configured to store the first value and the first indicator at the first memory location [write/store instruction includes data WDATA and address which goes to main cache store queue 212 via write port & signals/data/command paths including MS/STQ_ADDR - Bhoria fig 10a1-a2], and the controller is configured to responsively increment the first pointer [write pointer incremented– Halaharivi abstract]; wherein the first memory is configured to store the first read value at the second memory location [during RMW operation arbitration manager 414 issues read to main storage, read data and its ECC are provided to ECC logic 310, corrected and then sent to RMW pipeline including latches 402c-d, wherein the pipeline latches 402a-e are described as part of main cache store queue and hold values associated with pending write/store operations until arithmetic/RMW merge completes- Bhoria 0121, 0124 fig 4a], and the controller is configured to responsively increment the second pointer [special read pointer advanced when reading non-oldest entries - Halaharivi abstract]; and wherein the first memory is configured to read the first value and the first read value from the third memory location and to provide the first value and the first read value to the arithmetic pipeline [RMW merge obtains both new data (first value) and current word (first read value) and combines these operands to form updated data associated with queue entry that is at head of RMW queue - Bhoria 0121, 0124 fig 4a], and the controller is configured to responsively increment the third pointer [read pointer advances when oldest valid contents are read - Halaharivi abstract]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use three pointers in the invention of Bhoria/Cho as taught by Halaharivi because it would be advantageous for reducing read latency and improving SSD speed (Halaharivi 0004).
With respect to dependent claim 20 Bhoria/Cho/Halaharivi discloses a data forwarding block [write data forwarding – Bhoria fig 3c, 4b]; wherein the first memory, the arithmetic pipeline, and the write pipeline are configured to provide indicators to the data forwarding block [Bhoria fig 4b, 11b1-2]; wherein the data forwarding block is configured to compare an indicator provided from a memory location of the first memory to the indicator provided from the arithmetic pipeline or the write pipeline to determine whether there is a matching indicator [Bhoria fig 4b, 11b1-2]; wherein the data forwarding block is configured to, responsive to the matching indicator, provide a read value or result corresponding to the matching indicator to the first memory [Bhoria fig 4b, 11b1-2]; and wherein the first memory is configured to store the corresponding read value or corresponding result in the memory location of the first memory [Bhoria fig 4b, 11b1-2].
Claims 3, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bhoria/Cho in view of Kim et al (US PGPUB # 20230350809).
With respect to dependent claims 3, 11 Bhoria/Cho does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Kim discloses a table based command decoder having a third/buffer memory, using a decoding circuit to interpret commands and operable to handle multi-part messages – Kim abstract. Therefore, the combination of Bhoria/Cho/Kim discloses a third memory [data store 416 1116 - Bhoria 0112-0114, 0535]; and a decoding circuit [processing logic 302a-c, 306, 326 - Bhoria 0551-552]; wherein the decoding circuit is configured to: receive, in a message, either the first value, or the first indicator, or both [at least CPU interface receives store and RMW instructions comprising address/indicator, write data/value, size, etc - Bhoria 568; address related data may be processed separately (stored in pending store address datastore 416) from data in the store queue/latches] [different messages carrying different subsets of information such as a first command (control), later data (table), and a second command with index (partial address indication) and as such Kim’s decoding logic is operable to work with messages carrying such different information – Kim abstract] ; responsive to receiving both the first value and the first indicator in the message, provide the first value and the first indicator to the first memory; and responsive to receiving one of the first value or the first indicator in the message, provide the received one of the first value or the first indicator to the third memory [A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information – Kim abstract; stated another way, Kim teaches a third memory/buffer with an address table and a decoding circuit that decides where to place different parts of a multi-part message]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to receive, in a message, either the first value, or the first indicator, or both; responsive to receiving both the first value and the first indicator in the message, provide the first value and the first indicator to the first memory; and responsive to receiving one of the first value or the first indicator in the message, provide the received one of the first value or the first indicator to the third memory in the invention of Bhoria/Cho as taught by Kim because it would be advantageous for improving performance and overcoming possible degradation due to bandwidth shortage(s) in transferring commands and addresses (Kim 0005).
Claims 4, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bhoria/Cho/Kim in view of Lakshmanamurthy et al (US PGPUB # 20060069869).
With respect to dependent claims 4, 13 Bhoria/Cho/Kim does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Lakshmanamurthy teaches a first memory area (packet buffer), a second memory area (packet queue/descriptor), and a third memory area where a queue pointer is read, updated and written back. Therefore the combination of Bhoria/Cho/Kim/Lakshmanamurthy discloses wherein the third memory is configured to provide the first value and the first indicator to the first memory responsive to the third memory storing both the first value and the first indicator [A pointer is read referencing one end of the packet queue from a queue descriptor in the second memory area into a third memory area in one read operation. The pointer is updated in the third memory area to point to the added entry in the packet queue and the updated pointer in the third memory area is written to the queue descriptor in the second memory area in one write operation – Lakshmanamurthy abstract]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure a third memory to provide a first value and a first indicator to a first memory responsive to a third memory storing both the first value and the first indicator in the invention of Bhoria/Cho/Kim as taught by Lakshmanamurthy because it would be advantageous for minimizing memory bandwidth when queuing and dequeuing packet data (Lakshmanamurthy 0002-0004).
Claims 5, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bhoria/Cho in view of Favor (US PGPUB # 20020078302).
With respect to dependent claims 5, 14 Bhoria/Cho does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Favor teaches a cache retry request queue so that the combination of Bhoria/Cho/Favor discloses wherein a value or a result, and a corresponding indicator of a location in the second memory, together correspond to an update request [combination of a value or updated result and its address/indicator is the unit of update for main/victim storage - Bhoria fig 4a, paragraph 0126; “pending store address datastore 416 maintains a log of the addresses associated with each value stored in any of the latches 402a, 402b, 402c, 402d, 402e, and/or the merging circuits 403a, 403b, and/or 403c” and these addresses are associated with values that will be used to update main/victim cache]; and wherein a first pending update request is not stalled responsive to a second pending update request if the first memory is not full [an access request associated with a cache miss to a single cache line having a pending cache fill can be handled in a non-blocking manner by storing the cache miss in a retry queue while the cache fill is pending – Favor abstract ]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to avoid stalling a pending update request responsive to a second pending update request if the first memory is not full in the invention of Bhoria/Cho as taught by Favor because it would be advantageous/desirable for the cache memory to be able to continue to serve subsequent execution-unit access requests to any and all memory locations while a cache fill is in progress without stalling the execution-units (Favor 0007).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Bhoria/Cho/Kim in view of Kornegay et al (US PGPUB # 20090157970).
With respect to dependent claims 12 Bhoria/Cho does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Kornegay teaches receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache such that the combination of Bhoria/Cho/Kornegay discloses wherein the message includes an identifier of the processor [core ID associated with each cache line so that communication/messages between cores and shared cache can be associated with the correct core/processor - Kornegay abstract ]; and wherein the third memory is configured to store the first value or the first indicator in a memory location of the third memory corresponding to the identifier [buffer table in which address table stored and where entries are organized and accessed based on identifier/index – Kim abstract in view of Kornegay abstract teaching core ID associated with each cache line so that communication/messages between cores and shared cache can be associated with the correct core/processor]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include processor IDs for messages/communication in the invention of Bhoria/Cho/Kim as taught by Kornegay because it would be advantageous for optimizing cache management & improving the efficiency of a shared cache, and improve overall system performance, by dynamically providing more cache resources to cores whose applications can make good use of cache resources, while providing less cache resources to cores whose applications cannot benefit from the additional cache resources (Kornegay 0003).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KOTRA US PGPUB # 20230205693 teaches: Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host is disclosed. In an implementation, a memory controller identifies a first write instruction to write first data to a first memory location, where the first write instruction is not a processing-in-memory (PIM) instruction. The memory controller then writes the first data to a first PIM register. Opportunistically, the memory controller moves the first data from the first PIM register to the first memory location. In another implementation, a memory controller identifies a first memory location associated with a first read instruction, where the first read instruction is not a processing-in-memory (PIM) instruction. The memory controller identifies that a PIM register is associated with the first memory location. The memory controller then reads, in response to the first read instruction, first data from the PIM register.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-530p M-R.
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/Marwan Ayash/Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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