DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 10-13 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bell (US 2012/0151141) in view of Ramamoorthy (US 2017/0285995).
Claim(s) 1, 11 and 16, Bell teaches:
A method, comprising: determining that a size of a buffer of a solid state storage device of a storage system should be modified, wherein: [0031] FIG. 10 illustrates an embodiment of operations performed at the storage server 18 by the cache adjustment code 30 to process the server write activity levels received from the servers 2 to determine adjustments to make to the size of the write cache 32.
the solid state storage device comprises flash memory managed by a processing device external to the solid state storage device; [0021] The storage 6 may comprise storage media implemented in one or more storage devices known in the art, such as … solid state storage devices (e.g., EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, flash disk, storage-class memory (SCM)), electronic memory, etc. Fig. 1 and [0020] The storage server 18 includes a processor 22 and a memory 24 including a cache 26 to cache reads and writes from the servers 2 directed to the storage 6, server write activity information 28 including server write activity levels sent from the servers 2, and cache adjustment code 30 to process the gathered server write activity information 28 to determine whether to adjust a write cache 32 of the cache 26.
and changing the size of the buffer of the storage system. Fig. 10 and [0031] If (at block 206) the number of servers having the high write activity level exceeds a high number threshold, then the cache adjustment code increases (at block 208) the write cache 32 size, e.g., by an incremental amount or to a maximum write cache 32 size. [0031] If (at block 210) the number of servers having the medium number threshold is not met, then the cache adjustment code 30 determines (at block 214) whether the number of servers having the low write activity level exceeds a low number threshold. If so, then the cache adjustment code 30 decreases (at block 216) the write cache 32 size, such as by an incremental amount or to a minimum write cache size.
Bell does not explicitly teach, but Ramamoorthy teaches the buffer of the storage system comprises a portion of the flash memory; [0027] With reference to FIG. 1A, the storage array 102 includes disk storage 110 and a flash cache 112 (e.g., SSD). In one embodiment, one or more of the volumes in the disk storage are pinned volumes (e.g., volumes 2, 4, and 10), therefore, the data for these volumes is defined to be always kept in cache.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to combine the data storage system/method of Bell Jr., with the hybrid memory structure in storage devices taught by Ramamoorthy. The motivation for doing so would have been to enable the scaling of capacity and performance beyond the physical limitations of a single storage array by seamlessly clustering any combination of storage hybrid arrays. Also, an advantage of clustering is that performance can be managed to avoid capacity silos and performance hotspots, and enables easy management of all hardware resources across the cluster as a single storage entity. This is taught by Ramamoorthy in [0093].
Claim(s) 2, 12 and 17, Bell teaches:
wherein determining that the size of the buffer of the solid state storage device of the storage system should be modified comprises: determining that an amount of write activity in the storage system has increased above a first activity threshold; or determining that the amount of write activity in the storage system has decreased below a second activity threshold. Fig. 10 and [0031] If (at block 206) the number of servers having the high write activity level exceeds a high number threshold, then the cache adjustment code increases (at block 208) the write cache 32 size, e.g., by an incremental amount or to a maximum write cache 32 size.
Claim(s) 3, 13 and 18, Bell teaches:
wherein determining that the size of the buffer of the solid state storage device of the storage system should be modified comprises: determining that an amount of NVRAM utilization has increased above a first utilization threshold; or determining that the amount of NVRAM utilization has decreased below a second utilization threshold. Fig. 10 and [0031] If (at block 206) the number of servers having the high write activity level exceeds a high number threshold, then the cache adjustment code increases (at block 208) the write cache 32 size, e.g., by an incremental amount or to a maximum write cache 32 size. [0031] FIG. 1B shows the write path for a hybrid system with SSDs and HDDs, where the initiator 106 in the host 104 sends the write request to the network storage device, also referred to herein as storage array 102. As the write data comes in, the write data is written into NVRAM 108, and an acknowledgment is sent back to the initiator (e.g., the host or application making the request).
Claim(s) 10, Bell teaches:
wherein changing the size of the buffer of the storage system comprises: decreasing a portion of NVRAM of the solid state storage device used for the buffer. [0033] Further, the cache adjustment code 30 may provide multiple finer adjustments to the write cache size based on the determined level of write activity across all servers than described in FIG. 10, such as by increasing or decreasing the write cache size by incremental amounts up to a minimum or maximum write cache size. [0031] FIG. 1B shows the write path for a hybrid system with SSDs and HDDs, where the initiator 106 in the host 104 sends the write request to the network storage device, also referred to herein as storage array 102. As the write data comes in, the write data is written into NVRAM 108, and an acknowledgment is sent back to the initiator (e.g., the host or application making the request).
Claim(s) 4-9, 14, 15, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bell (US 2012/0151141) and Ramamoorthy (US 2017/0285995), further in view of Tanpairoj (US 2019/0065080).
Claim(s) 4, 14 and 19, the combination of Bell and Ramamoorthy does not explicitly teach, but Tanpairoj teaches:
wherein changing the size of the buffer of the storage system comprises: increasing a portion of SLC flash memory of the solid state storage device used for the buffer. [0065] The firmware of the memory device may monitor the LBA usage of the memory devices and when the memory device exceeds the thresholds the firmware may reconfigure memory cells from SLC to MLC or from MLC to SLC thus changing the size of the SLC cache.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to combine the data storage system/method of Bell Jr. and Ramamoorthy, with the SLC cache management system/method taught by Tanpairoj. The motivation for doing so would have been to provides a balance between the speed of SLC memory cells with the storage capacity of MLC memory cells. This is taught by Tanpairoj in [0059].
Claim(s) 5, Tanpairoj teaches:
wherein increasing the portion of the SLC flash memory comprises: operating a portion of the QLC flash memory of the solid state storage device in an SLC mode. [0065] The firmware of the memory device may monitor the LBA usage of the memory devices and when the memory device exceeds the thresholds the firmware may reconfigure memory cells from SLC to MLC or from MLC to SLC thus changing the size of the SLC cache. [0008] MLC can refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a triple-level cell (TLC) can refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) can store four bits of data per cell.
Claim(s) 6, Tanpairoj teaches:
wherein the portion of the QLC flash memory that is operated in SLC mode is selected based on amounts of wear in cells of the QLC flash memory. [0097] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to the memory device with each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., a value, characteristic) in response to the wear cycle information.
Claim(s) 7, 15 and 20, Tanpairoj teaches:
wherein changing the size of the buffer of the storage system comprises: decreasing a portion of SLC flash memory of the solid state storage device used for the buffer. [0065] The firmware of the memory device may monitor the LBA usage of the memory devices and when the memory device exceeds the thresholds the firmware may reconfigure memory cells from SLC to MLC or from MLC to SLC thus changing the size of the SLC cache.
Claim(s) 8, Tanpairoj teaches:
wherein decreasing the portion of the SLC flash memory used for the buffer comprises: operating a portion of the QLC flash memory of the solid state storage device in a QLC mode. [0065] The firmware of the memory device may monitor the LBA usage of the memory devices and when the memory device exceeds the thresholds the firmware may reconfigure memory cells from SLC to MLC or from MLC to SLC thus changing the size of the SLC cache. [0008] MLC can refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a triple-level cell (TLC) can refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) can store four bits of data per cell.
Claim(s) 9, Tanpairoj teaches:
wherein a portion of the SLC flash memory used for the buffer comprises a roving region for the SLC flash memory. [0035] Fig. 2 In addition, reserved space R is flash space reserved or allocated for general purpose use of unpinned volumes and system resources (e.g., metadata caching). In addition, overprovisioning space O is flash space that is not pinnable, besides the reserved/allocated space R. [0065] The firmware of the memory device may monitor the LBA usage of the memory devices and when the memory device exceeds the thresholds the firmware may reconfigure memory cells from SLC to MLC or from MLC to SLC thus changing the size of the SLC cache.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1-20 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-10 of U.S. Patent No. 12229437. Although the claims at issue are not identical, they are not patentably distinct from each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yun (US 2019/0250858): discloses memory controller configured to determine whether the capacities of the input buffer and the output buffer are to be changed by comparing the buffer analysis data and the threshold value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133
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