DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11, 13-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2015/0228346).
Consider claim 1, Choi et al. discloses a storage device comprising: a storage controller configured to transmit a command and an address via a command/address line, the command/address line being separate from a data line; and a non-volatile memory device configured to exchange a first data with the storage controller via the data line and exchange a second data in synchronization with the first data via the command/address line, the second data including a plurality of sub-data, the plurality of sub- data comprising auxiliary information associated with the first data, wherein the storage controller is configured to transmit, via the command/address line, a sub-address associated with selecting at least one of the plurality of sub-data in synchronization with the first data to the non-volatile memory device, wherein the non-volatile memory device is configured to exchange, via the command/address line and in synchronization with the first data, a sub-data identified based on the sub-address from among the plurality of sub-data (abstract, Fig. 4-7, [0029], [0037], [0048], Choi et al. discloses a non-volatile memory system with a command, address and data line. Depending on the command, a multitude of data can be written or read. The system is synchronized with a clock. Setting values are also sent that control the operation of the memory for the command. The command and address lines include a plurality of addresses (sub-addressed) and setting values (sub-data which includes auxiliary information). The addresses and setting values are related. Further data can be read out if the command is a read based on the data sent to the non-volatile memory. ).
Consider claim 2, Choi et al. discloses the storage device of claim 1, wherein the least one of the plurality of sub-data include at least one of a soft decision data associated with the first data, a compressed data of the soft decision data, a bit count of a logic value included in the first data, a temperature information, an attribute data of the first data, and a reliability data (abstract, Fig. 4-7, [0029], [0037], [0048], the setting values are used to control the operation of the memory and are therefore at least considered reliability data.).
Consider claim 3, Choi et al. discloses the storage device of claim 1, wherein the least one of the plurality of sub-data include at least one of a stream information, an importance information, and a reliability information of the first data (abstract, Fig. 4-7, [0029], [0037], [0048], the setting values are used to control the operation of the memory and are therefore at least considered reliability data.).
Consider claim 4, Choi et al. discloses the storage device of claim 1, wherein the sub-address is included in a plurality of sub-addresses, and the second data is determined according to a last sub-address inputted among the plurality of sub-addresses inputted before the second data is outputted (abstract, Fig. 4-7, [0029], [0037], [0048], there can be multiple setting values set and the setting values are used in accessing the memory.).
Consider claim 5, Choi et al. discloses the storage device of claim 1, wherein the sub-address is inputted to the non-volatile memory device following a column address and a row address (abstract, Fig. 4-7, [0029], [0037], [0048], Choi et al., discloses column and row addressing.).
Consider claim 6, Choi et al. discloses the storage device of claim 1, wherein the command, the address, and the sub- address are transmitted to the non-volatile memory device in a packet including a header part and a body part (abstract, Fig. 4-7, [0029], [0037], [0048], the CMD start, addresses, setting values and Confirm CMD are considered to be a packet of information sent for execution.).
Consider claim 7, Choi et al. discloses the storage device of claim 6, wherein a bit value of the header part is defined according to a transmission direction of the packet transmitted to the command/address line (abstract, Fig. 4-7, [0029], [0037], [0048], the CMD start, and addresses provide direction as to what is to be performed and where.).
Consider claim 8, Choi et al. discloses the storage device of claim 7, wherein the body part of the packet corresponding to the sub-address includes selection information of the second data (abstract, Fig. 4-7, [0029], [0037], [0048], the settings value and command confirm is selection information for accessing data.).
Consider claim 9, Choi et al. discloses non-volatile memory device, comprising: a cell array including a memory area is configured to be selected by a first address; a page buffer configured to sense a read data from the selected memory area; a sub-data register configured to store a plurality of sub-data corresponding to the read data; a control circuit configured to provide a second address associated with selecting at least one of the plurality of sub-data to the sub-data register, the plurality of sub-data comprising auxiliary information associated with the read data; and an input/output circuit configured to receive the first address and the second address through a command/address line, the command/address line being separate from a data line, provide the first address and the second address to the control circuit, and output a selected sub-data of the plurality of sub-data to the command/address line in synchronization with the output of the read data, wherein the control circuit is configured to exchange, through the command/address line and in synchronization with the read data, a sub-data identified based on the second address from among the plurality of sub-data. (abstract, Fig. 4-7, [0029], [0032], [0037], [0041], [0048], [0079]-[0081], Choi et al. discloses a non-volatile memory system with a command, address and data line. Depending on the command, a multitude of data can be written or read. The system is synchronized with a clock. Setting values are also sent that control the operation of the memory for the command. The command and address lines include a plurality of addresses (sub-addressed) and setting values (sub-data which includes auxiliary information). The addresses and setting values are related. Further data can be read out if the command is a read based on the data sent to the non-volatile memory. Page and data buffers are disclosed along with parameter registers.).
Consider claim 10, Choi et al. discloses the non-volatile memory device of claim 9, wherein the plurality of sub-data includes at least one of a soft decision data associated with read data, a compressed data of the soft decision data, a bit count of a logic value included in the read data, a temperature information, an attribute data, and a reliability data of the read data (abstract, Fig. 4-7, [0029], [0037], [0048], the setting values are used to control the operation of the memory and are therefore at least considered reliability data.).
Consider claim 11, Choi et al. discloses the non-volatile memory device of claim 9, wherein the second address is included in a read command set provided through the command/address line, and the second address is transmitted to the input/output circuit subsequent to the first address (abstract, Fig. 4-7, [0029], [0037], [0048], a read command can be issues with multiple addresses as in Fig. 6.).
Consider claim 13, Choi et al. discloses the non-volatile memory device of claim 9, wherein a command, the first address, and the second address transmitted to the input/output circuit through the command/address line are provided in a packet, the packet including a header part and a body part (abstract, Fig. 4-7, [0029], [0037], [0048], the CMD start, addresses, setting values and Confirm CMD are considered to be a packet of information sent for execution.).
Consider claim 14, Choi et al. discloses the non-volatile memory device of claim 13, wherein the second address is set to a packet header part different from the first address (abstract, Fig. 4-7, [0029], [0037], [0048], the CMD start, and addresses provide direction as to what is to be performed and where. The addresses are separate.).
Consider claim 15, Choi et al. discloses the non-volatile memory device of claim 9, wherein the input/output circuit receives a command/address clock signal associated with receiving a command, the first address, and the second address transmitted through the command/address line (abstract, Fig. 4-7, [0029], [0037], [0048], Choi et al. discloses a non-volatile memory system with a command, address and data line. Depending on the command, a multitude of data can be written or read. The system is synchronized with a clock.).
Consider claim 16, Choi et al. discloses a method of operating a non-volatile memory device, comprising: receiving a command, a first address, and a second address through a command/address line, the command/address line separate from a data line; sensing a read data corresponding to the first address; selecting, among the plurality of sub-data and based on the second address, at least one of a plurality of sub-data, the plurality of sub-data comprising auxiliary information associated with the read data; outputting the read data through the data line; and outputting the at least one of a plurality of sub-data, identified based on the second address, in synchronization with the output of the read data through the command/address line. (abstract, Fig. 4-7, [0029], [0032], [0037], [0041], [0048], [0079]-[0081], Choi et al. discloses a non-volatile memory system with a command, address and data line. Depending on the command, a multitude of data can be written or read. The system is synchronized with a clock. Setting values are also sent that control the operation of the memory for the command. The command and address lines include a plurality of addresses (sub-addressed) and setting values (sub-data which includes auxiliary information). The addresses and setting values are related. Further data can be read out if the command is a read based on the data sent to the non-volatile memory.).
Consider claim 19, Choi et al. discloses the method of claim 16, further comprising: receiving a command/address clock signal associated with receiving at least one of the command, the first address and the second address transmitted through the command/address line (abstract, Fig. 4-7, [0029], [0037], [0048], Choi et al. discloses a non-volatile memory system with a command, address and data line. Depending on the command, a multitude of data can be written or read. The system is synchronized with a clock.).
Consider claim 20, Choi et al. discloses the method of claim 16, wherein the command, the first address, and the second address are inputted through the command/address line in the form of a packet including a header part and a body part (abstract, Fig. 4-7, [0029], [0037], [0048], the CMD start, addresses, setting values and Confirm CMD are considered to be a packet of information sent for execution.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2015/0228346) as applied to claims 9 and 16 above, and further in view of Klint et al. (US 2006/0230250).
Consider claim 12, Choi et al. discloses the non-volatile memory device of claim 9, however Choi et al. does not explicitly teach: “further comprising: a sub-data generator configured to generate the plurality of sub-data from the read data sensed by the page buffer.”. But, Klint et al, which is also directed to a non-volatile memory system similar to Choi et al. where parameter/status information, like those described in Choi et al. are determined by sending a command to the memory to receive its latency set range and have this value set in a register (Klint et al.: Fig. 3 and [0056]-[0062]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the system of Choi et al. to read of status information and store/generate that information as is done in Klint et al. because doing so allows for more versatility by allowing multiple types of memory to be used in the system and for the command communication to adjust based on the type of memory being used in the system (Klint et al.: [0010]).
Consider claim 17, Choi et al. discloses the non-volatile memory device of claim 16, however Choi et al. does not explicitly teach: “further comprising: generating the plurality of sub-data from the read data to store the plurality of sub- data in a sub-data register.”. But, Klint et al, which is also directed to a non-volatile memory system similar to Choi et al. where parameter/status information, like those described in Choi et al. are determined by sending a command to the memory to receive its latency set range and have this value set in a register (Klint et al.: Fig. 3 and [0056]-[0062]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the system of Choi et al. to read of status information and store/generate that information as is done in Klint et al. because doing so allows for more versatility by allowing multiple types of memory to be used in the system and for the command communication to adjust based on the type of memory being used in the system (Klint et al.: [0010]).
Consider claim 18, Choi et al. discloses the non-volatile memory device of claim 17, wherein the plurality of sub-data include at least one of a soft decision data associated with the read data, a compressed data of the soft decision data, a bit count of a logic value included in the read data, a temperature information, an attribute data, and a reliability data of the read data (abstract, Fig. 4-7, [0029], [0037], [0048], the setting values are used to control the operation of the memory and are therefore at least considered reliability data.).
Response to Arguments
Applicant’s arguments filed 6/10/2026 have been fully considered but they are not persuasive. The arguments pertain to the new claim limitations which have been addressed in the appropriate claim rejections above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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