Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 2/14/2025 and 2/27/2026 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12259817. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application and patents claim a smart storage device with a smart interface that communicates with an accelerator circuit, a storage controller, non-volatile memory device, host device, and memory device with a cache-coherent interconnect protocol.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, line 12, “the internal bus” lacks proper antecedent basis since it was not mentioned previously.
In claim 10, lines 10 and 11, it is not clear the difference between a non-volatile memory device or a memory device since a non-volatile memory device is also a memory device.
In claim 17, line 6, it is not clear whether the accelerator circuit is the same one as in line 2 or another one.
In claim 17, lines 10 and 11, it is not clear what is meant by “performing,…., the first data access for a first data to…”.
In claim 17, lines 10-15, it is not clear the difference between a non-volatile memory device or a memory device since a non-volatile memory device is also a memory device.
In claim 18, line 3, it is not clear if the first data access being performed is the same as the first data access that was performed in claim 17.
In claim 18, lines 5 and 6, it is not clear what is meant by “transmitting…to the acceleration computation”.
In claim 18, line 7, it is not clear whether the acceleration computation is the same one as in line 6 or another one.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Agarwal (U.S. Publication No. 2020/0012604 A1), hereafter referred to as Agarwal’604.
Referring to claim 1, Agarwal’604, as claimed, an operating method for a smart storage device (see Fig. 1), the operating method comprising: receiving a computation command (processing and memory capabilities such as graphics functionalities, coherent requests and memory flows with host processor 145, see para. [0019]; also note: command, computations, see para. [0054]) from a host device (computing devices such as portable device or server system, see paras. [0050], [0053], Figs 7-9) and transmitting the computation command to an accelerator circuit (accelerator logic 125, see Fig. 1; also note: Accelerators 750a-b, see Fig. 7, accelerators 950 960, see Fig. 9) through a smart interface (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]); decoding (decoder, see paras. [0027], [0033], [0061], [0079]), by the accelerator circuit, the computation command and requesting data access to a storage controller through an internal connection bus based on the decoded computation information (see Figs. 1, 7-9); performing, by the storage controller, data access to a non-volatile memory device of the smart storage device (in response to incoming write requests/transactions, perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]); and receiving, by the accelerator circuit, the data access result from the non-volatile memory device and performing an acceleration computation based on the computation command (accelerator logic and circuitry provide processing and memory capabilities based on the device such as graphics functionality, see para. [0019]), wherein the internal connection bus directly connects the accelerator circuit and the storage controller, and the internal bus is not directly connected to the host device (DMA circuits may send direct stores to device 105 for storage in accelerator memory without performing a prefetch operation to obtain ownership. In this way, embodiments may avoid a bias flip from device bias to host bias for data of such incoming write requests, optimizing processing flow and reducing traffic between host processor 145 and device 105, see paras. [0020], [0021]; also note: point to point interfaces, see paras. [0056], [0057], Figs. 7 and 9).
As to claim 2, Agarwal’604 also discloses the smart interface is configured to connect (link 189, see Fig. 1 and para. [0018]; also note: plurality of interconnects 730a-b, see Fig. 7; interconnect 812, see Fig. 8, CXL buses 942, 944, see Fig. 9) between the host and the accelerator circuit through a cache-coherent interconnect shared memory region cache protocol (cache protocol) (interconnects supporting CXL.cache, see para. [0018]) and a cache-coherent interconnect memory pooling and expansion protocol (mem protocol) (interconnects supporting CXL.mem, see para. [0018]).
As to claim 3, Agarwal’604 also discloses the computation information includes a computation type (type, see paras. [0023], [0050], [0053], [0054], [0084]) and an address of data necessary for the computation (address, see paras. [0060], [0061], [0064], [0078], [0079]).
As to claim 4, Agarwal’604 also discloses the performing, by the storage controller, data access is configured to: receive a first access request from the host device (in response to incoming write requests/transactions, perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]) and a second access request from the accelerator circuit, schedule an operation sequence according to a preset policy (policy, see paras. [0031], [0056], and Fig. 3), and perform data access operation in order of the scheduled operation sequence (direct stores to device 105 for storage in memory 130, see para. [0021]; also note: DMA circuit configured to optimize incoming DMA write requests such that they may be directly forwarded to an external device-attached memory, see paras. [0053], [0078], and Fig. 8).
As to claim 5, Agarwal’604 also discloses after the receiving the data access result, the accelerator circuit performs first coherence processing (maintaining coherency, see paras. [0037]-[0041]; also note: accelerator logic and circuitry communicate using a coherent interconnect protocol for various functions such as coherent requests and memory flows with host processor, see para. [0019]) with the host device to store a first data in the accelerator memory (data from accelerator circuit stored in accelerator memory 130, see Fig. 1 and para. [0020]) through the cache protocol (interconnects supporting CXL.cache, see para. [0018]).
As to claim 6, Agarwal’604 also discloses after the performing the acceleration computation, the accelerator circuit performs second coherence processing with the host device (maintaining coherency, see paras. [0037]-[0041]; also note: accelerator logic and circuitry communicate using a coherent interconnect protocol for various functions such as coherent requests and memory flows with host processor, see para. [0019]) and stores a second data generated by the acceleration computation in the accelerator memory (data from accelerator circuit stored in accelerator memory 130, see Fig. 1 and para. [0020]).
As to claim 7, Agarwal’604 also discloses when the second coherence processing and the storing the second data are completed, the accelerator circuit transmits a completion message to the host device through the smart interface (completion, see paras. [0037], [0042], [0044], [0046], [0048], [0070] and Fig. 5).
As to claim 8, Agarwal’604 also discloses the completion message includes the second data or a value set based on the second data (completion, see paras. [0037], [0042], [0044], [0046], [0048], [0070] and Fig. 5).
As to claim 9, Agarwal’604 also discloses the smart interface is configured to connect between the host and the storage controller through a cache-coherent interconnect device discovery, configuration, and I/O operations protocol (IO protocol) (interconnects supporting CXL.io, see para. [0018]; also note: maintaining coherency, see paras. [0037]-[0041]; using a coherent interconnect protocol for various functions such as coherent requests and memory flows with host processor, see para. [0019]).
Referring to claim 10, Agarwal’604, as claimed, an operating method of a smart storage device, the operating method comprising: receiving an access command (in response to incoming write requests/transactions, perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]) from a host device via a smart interface (computing devices such as portable device or server system, see paras. [0050], [0053], Figs 7-9), which the smart interface includes an internal connection bus directly connecting a first data bus (plurality of interconnects 730a-b, see Fig. 7; interconnect 812, see Fig. 8, CXL buses 942, 944, see Fig. 9; also note: link 189, see Fig. 1 and para. [0018]) conforming to a cache-coherent interconnect memory pooling and expansion protocol (mem protocol) (interconnects supporting CXL.mem, see para. [0018]) and a cache-coherent interconnect device discovery, configuration, and I/O operations protocol (IO protocol) (interconnects supporting CXL.io, see para. [0018]) and a second data bus (plurality of interconnects 730a-b, see Fig. 7; interconnect 812, see Fig. 8, CXL buses 942, 944, see Fig. 9; also note: link 189, see Fig. 1 and para. [0018]) conforming to the IO protocol to directly access a memory controller circuit (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]) and a storage controller (see Figs. 1 and 7-9); checking, by the smart interface, a protocol of the access command; parsing, by the smart interface, the access command (receive write request and based at least in part on an address of the write request, to directly send the write request to a device, see paras. [0020], [0021], [0078]-[0082], Figs. 8 and 9) when the checked protocol is the IO protocol (interconnects supporting CXL.io, see para. [0018]) and checking whether an address information belongs to a non-volatile memory device or a memory device (access various memories such as accelerator memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056], see para. [0021], Figs. 1 and 8); receiving, by a storage controller, the access command via the second data bus and performing access operation in the non-volatile memory device based on the address information when the address information is for the non-volatile memory device (processing and memory capabilities such as graphics functionalities, coherent requests and memory flows with host processor 145, see para. [0019]; also note: accelerator memory 130, see para. [0021] and Fig. 1; also note: various memories such as device memory, host cache memory, host memory, see Figs. 1 and 7-9); transmitting, by the smart interface, the access command from the second data bus to first data bus through the internal connection bus when the address information is for the memory device (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]); and performing, by a memory controller, the access operation in the memory device based on the transmitted access command and the address information, wherein the internal connection bus is not directly connected to the host device (DMA circuits may send direct stores to device 105 for storage in accelerator memory without performing a prefetch operation to obtain ownership. In this way, embodiments may avoid a bias flip from device bias to host bias for data of such incoming write requests, optimizing processing flow and reducing traffic between host processor 145 and device 105, see paras. [0020], [0021]; also note: point to point interfaces, see paras. [0056], [0057], Figs. 7 and 9).
As to claim 11, Agarwal’604 also discloses the memory controller performs and complete the access operation (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]) and send a completion message to the host device through the smart interface (completion, see paras. [0037], [0042], [0044], [0046], [0048], [0070] and Fig. 5).
As to claim 12, Agarwal’604 also discloses the smart interface includes a router (interface logic and circuitry to enable multi-protocol communication between components of host and devices in accordance with one or more interconnect protocols dynamically; multiplexers implement arbitration circuitry to arbitrate between communications of different protocols and provide selected communications to a physical layer, see paras. [0023]-[0025], Figs. 1 and 7-9), a memory protocol handler (interconnects supporting CXL.mem, see para. [0018]), and a storage protocol handler (perform requests/transactions to/from memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]; also note second request, see paras. [0073] and [0080] and Figs. 1 and 7-9).
As to claim 13, Agarwal’604 also discloses when the address information belongs to an address of the memory device, the storage protocol handler transfers the access command to the memory protocol handler through the internal connection bus (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]).
As to claim 14, Agarwal’604 also discloses when the checked protocol is the mem protocol by the smart interface, wherein the memory controller performs the access operation in the memory device (perform requests/transactions to/from memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]; also note second request, see paras. [0073] and [0080] and Figs. 1 and 7-9) and notifies the memory protocol handler of the performance result, and wherein the memory protocol handler transfers the performance result to the host device (completion, see paras. [0037], [0042], [0044], [0046], [0048], [0070] and Fig. 5).
As to claim 15, Agarwal’604 also discloses when the parsed access command requests to read the data in the memory device, wherein the memory protocol handler receives a data access command based on the parsed access command and requests data access to the memory controller(receive write request and based at least in part on an address of the write request, to directly send the write request to a device, see paras. [0020], [0021], [0078]-[0082], Figs. 8 and 9), and wherein the memory controller reads the data from the memory device (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]).
As to claim 16, Agarwal’604 also discloses the storage controller receives the data from the memory controller through the internal connection bus and writes the data to the storage device (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]).
As to claim 17, Agarwal’604 also discloses an operating method of a smart storage device, wherein the smart storage device includes an accelerator circuit (accelerator logic and circuitry provide processing and memory capabilities based on the device such as graphics functionality, see para. [0019]), a storage controller, a memory controller and a smart interface, wherein the operating method comprises: receiving, by the smart interface, a computation command (processing and memory capabilities such as graphics functionalities, coherent requests and memory flows with host processor 145, see para. [0019]; also note: command, computations, see para. [0054]) from a host device (computing devices such as portable device or server system, see paras. [0050], [0053], Figs 7-9) and transmitting the computation command to an accelerator circuit (accelerator logic 125, see Fig. 1; also note: Accelerators 750a-b, see Fig. 7, accelerators 950 960, see Fig. 9) through a smart interface (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]); decoding (decoder, see paras. [0027], [0033], [0061], [0079]), by the accelerator circuit, the computation command and requesting first data access to a storage controller through a first internal connection bus based on the decoded computation information (see Figs. 1, 7-9); performing, by the storage controller, the first data access for a first data to a non- volatile memory device of the smart storage device (in response to incoming write requests/transactions, perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]); requesting, by the storage controller, a second data access for a second data to a memory device (direct stores to device 105 for storage in memory 130, see para. [0021]; also note: DMA circuit configured to optimize incoming DMA write requests such that they may be directly forwarded to an external device-attached memory, see paras. [0053], [0078], and Fig. 8) in response to a determination that accessing to the memory device is necessary for processing the first data (accelerator logic and circuitry provide processing and memory capabilities based on the device such as graphics functionality, see para. [0019]); transmitting, by the smart interface, the second data access to the memory device through a second internal connection bus based on the request from the storage controller (in response to incoming write requests/transactions, perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]); and performing, by the memory controller, memory access operation for the first data in the memory device (direct stores to device 105 for storage in memory 130, see para. [0021]; also note: DMA circuit configured to optimize incoming DMA write requests such that they may be directly forwarded to an external device-attached memory, see paras. [0053], [0078], and Fig. 8), wherein the first internal connection bus and the second internal connection bus are not directly connected to the host device (DMA circuits may send direct stores to device 105 for storage in accelerator memory without performing a prefetch operation to obtain ownership. In this way, embodiments may avoid a bias flip from device bias to host bias for data of such incoming write requests, optimizing processing flow and reducing traffic between host processor 145 and device 105, see paras. [0020], [0021]; also note: point to point interfaces, see paras. [0056], [0057], Figs. 7 and 9).
Note claim 18 recites similar limitations of claim 1. Therefore it is rejected based on the same reason accordingly.
Note claim 19 recites similar limitations of claim 10. Therefore it is rejected based on the same reason accordingly.
As to claim 20, Agarwal’604 also discloses the storage controller and the memory controller perform and complete the first data access operation and the second data access operation (perform direct writes to memory 130 and device-attached memory, see paras. [0020], [0021], [0031], [0038], [0046], [0052], [0053], [0056]) and send completion message to the host device through the smart interface (completion, see paras. [0037], [0042], [0044], [0046], [0048], [0070] and Fig. 5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Marolia et al. (U.S. Publication No. 2019/0042518 A1) discloses platform interface layer and protocol for accelerators.
Cohen et al. (U.S. Publication No. 2020/0081660 A1) discloses I/O device and computing host interoperation.
Samynathan et al. (U.S. Publication No. 2020/0301898 A1) discloses systems for accelerating data operations by utilizing dataflow subgraph templates.
Bleiweiss et al. (U.S. Publication No. 2019/0205736 A1) discloses compute optimization for deep neural networks.
DOSHI et al. (U.S. Publication No. 2021/0117249 A1) discloses infrastructure processing unit that to expose infrastructure services to be accessed by microservices for function composition.
Modukuri et al. (U.S. Patent No. 11,132,326 B1) discloses techniques to transfer data among hardware devices.
Malladi et al. (U.S. Publication No. 2021/0373951 A1) discloses system for composable coherent devices.
Makaram et al. (U.S. Publication No. 2020/0328879 A1) discloses secure communications over computer buses.
Das Sharma (U.S. Publication No. 2021/0240655 A1) discloses source ordering in device interconnects.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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