DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of information disclosure statement filed 14 February 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Krah et al; (Publication number: US 2023/0094533 A), hereafter Krah.
Regarding claim 13:
Krah discloses a micro-LED display device (Krah ABSTRACT; Figure 1A – 1E) comprising:
a display panel (Krah Figure 2A 202) including:
a plurality of pixel circuits for driving of a plurality of micro-LEDs (Krah Figure 5B drivers 526 for pixels in each ITO bank; Figure 2A microLEDs 206; [0066][0089]); and
a micro-driver configured to control an operation of each of the plurality of pixel circuits, first to 16th row cathode electrodes extending in a row direction of the display panel and spaced from each by a predefined spacing in a column direction (Krah Figure 5A see 1 – 16th rows of ITO banks 506 extending the X-direction; [0066] each ITO back serves as cathode electrode); and a micro-driver between a column-directional arrangement of the first to 8th row cathode electrodes and a column-directional arrangement of the ninth to 16th row cathode electrode (Krah Figure 5A a display chiplet 514B is disposed as claimed).
Claim(s) 19 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Charisoulis et al; (Publication number: US 2023/0086380 A1), hereafter Charisoulis.
Regarding claim 19:
Charisoulis discloses a micro-LED display device (Charisoulis Figure 1) comprising:
a display panel (Charisoulis Figure 1 18) including:
a plurality of pixel circuits configured to drive a plurality of micro-LEDs (Charisoulis Figure 9 105); and
a micro-driver configured to control an operation of each of the plurality of pixel circuits (Charisoulis microdriver 78), wherein each of the plurality of pixel circuits include:
a driving transistor configured to supply a power voltage in response to a gate driving voltage (Charisoulis Figure 8 second transistor 106B);
a first transistor configured to constitute a current path together with the driving transistor in response to a light-emission signal (Charisoulis Figure 8 first transistor 106A);
first to eight micro-LEDs, each having an anode electrode connected to the first transistor (Charisoulis Figure see micro-driver 78 connected to subpixels 82); and
a switch circuit configured to selectively connect each of the cathode electrodes of the first to eight micro-LEDs to a power line for a negative voltage or a vias voltage (Charisoulis Figure 9 decoder 130 connects VNEG or Vbias to cathode of diode). Regarding claim 20: Charisoulis discloses the micro-LED display device of claim 19, wherein the switch circuit is configured to the negative voltage to a cathode of the micro-LED to emit light, and to apply the bias voltage to a cathode electrode of each of remaining micro-LEDs not to emit light (Charisoulis [0053]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5, 6 – 9, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over KRAH et al; (Publication number: US 2023/0094533 A1), hereafter Krah, in view of Kim et al; (Publication number: US 2012/0162176 A1), hereafter Kim.
Regarding claim 1:
Krah discloses a micro-LED display device (Krah ABSRACT; Figure 1A – 1E) comprising:
a display panel (Krah Figure 2A 202) including:
a plurality of pixel circuits configured to drive a plurality of micro-LEDs (Krah Figure 5B pixel comprises pixels circuits in each ITO bank; Figure 2A microLEDs 206; [0066][0089]); and
a micro-driver configured to control an operation of each of the plurality of pixel circuits (Krah Figure 2A touch and display IC 212)
Krah does not disclose:
power management circuit configured to manage a level of a bias voltage so that a gap voltage as a difference between a negative voltage and the bias voltage used to selectively drive one of the plurality of micro-LEDs is maintained at a value lower than a threshold voltage of each of the plurality of micro- LEDs.
However, Kim discloses pixel and organic light emitting display device using the same. More particularly, Kim discloses a power management circuit (Kim Figure 6 power source supply 400) configured to manage a level of a bias voltage (Kim Figure 6 -Vbias) so that a gap voltage as a difference between a negative voltage (Kim ELVSS) and the bias voltage used to selectively drive one of a plurality of LEDs is maintained at value lower than a threshold voltage of each of the plurality of LEDs (Kim Figure 3 transistor M3 is diode connected and applied negative bias volage at node N20).
It would have been obvious to modify Krah to include power management circuit configured to manage a level of a bias voltage so that a gap voltage as a difference between a negative voltage and the bias voltage used to selectively drive one of the plurality of micro-LEDs is maintained at a value lower than a threshold voltage of each of the plurality of micro- LEDs, as claimed. Those skilled in the art would appreciate the ability to reduce a leakage current in the light emitting diode when light is not emitted (Kim [0046]).
Regarding claim 5:
Krah (in view of Kim) discloses the micro-LED display device of claim 1, wherein the negative voltage is applied to a cathode electrode of a micro-LED from the plurality of micro-LEDs to emit light, the bias voltage is applied to the cathode electrode of a micro-LED from the plurality of micro-LEDs to not emit light, and the bias voltage is higher than the negative voltage (Kim Figure 3 -Vbias is applied to cathode through OLED element; Vbias voltage is more negative than ELVSS).
Regarding claim 6:
Krah (in view of Kim) discloses the micro-LED display device of claim 1, wherein the display panel includes: first to 16th row cathode electrodes spaced from each other by predetermined spacing in a column direction, wherein each of first to 16th row cathode electrode extends in a row direction of the display panel (Krah Figure 5A see 1 – 16th rows of ITO banks 506 extending the X-direction; [0066] each ITO back serves as cathode electrode), wherein the micro-driver is between a column-directional arrangement of the first to 8th row cathode electrodes and a column-directional arrangement of ninth to 16th row cathode electrodes (Krah Figure 5A a display chiplet 514B is disposed as claimed).
Regarding claim 7:
Krah (in view of Kim) discloses the micro-LED display device of claim 6, wherein the plurality of pixel circuits are one each of the first to 16th row cathodes electrodes and are spaced from each other by a predetermined spacing in a row direction (Krah Figure 5B pixel circuits are located on ITO banks 506; predetermined spacing illustrated Figure 4).
Regarding claim 8:
Krah (in view of Kim) discloses the micro-LED display device of claim 7, wherein the micro-driver is connected to each of the plurality of pixel circuits via a first anode electrode line and a second anode electrode line (Krah Figure 5F illustrates for example electrodes lines C and D).
Regarding claim 9:
Krah (in view of Kim) discloses the micro-LED display device of claim 8, wherein the plurality of pixel circuits include: first to eight micro-LEDs connected to the micro-driver via first anode electrode lines, respectively; and first to eight redundancy micro-LEDs connected to the micro-driver via second anode electrode lines, respectively (Krah Figure 5F – [0075]).
Regarding claim 14:
Krah does not disclose the micro-LED display device of claim 13, further comprising: a power management circuit configured to manage a level of a bias voltage so that a gap voltage difference between a negative voltage and the bias voltage used to selectively drive one of the plurality of micro-LEDs is maintained at a value lower than a threshold voltage of each of the plurality of micro-LEDs.
However, Kim discloses pixel and organic light emitting display device using the same. More particularly, Kim discloses a power management circuit (Kim Figure 6 power source supply 400) configured to manage a level of a bias voltage (Kim Figure 6 -Vbias) so that a gap voltage as a difference between a negative voltage (Kim ELVSS) and the bias voltage used to selectively drive one of a plurality of LEDs is maintained at value lower than a threshold voltage of each of the plurality of LEDs (Kim Figure 3 transistor M3 is diode connected and applied negative bias volage at node N20).
It would have been obvious to modify Krah to include power management circuit configured to manage a level of a bias voltage so that a gap voltage as a difference between a negative voltage and the bias voltage used to selectively drive one of the plurality of micro-LEDs is maintained at a value lower than a threshold voltage of each of the plurality of micro- LEDs, as claimed. Those skilled in the art would appreciate the ability to reduce a leakage current in the light emitting diode when light is not emitted (Kim [0046]).
Regarding claim 15:
Kim (in view of Krah) discloses the micro-LED display device of claim 14, wherein the negative voltage is applied to a cathode electrode of a micro-LED from the plurality of micro-LEDs to emit light, the bias voltage is applied to the cathode electrode of a micro-LED from the plurality of micro-LEDs to not emit light, and the bias voltage is higher than the negative voltage (Kim Figure 3 -Vbias is applied to cathode through OLED element; Vbias voltage is more negative than ELVSS).
Claim(s) 20 - 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Charisoulis et al; (Publication number: US 2023/0086380 A1), hereafter Charisoulis, in view of Kim et al; (Publication number: US 2012/0162176 A1), hereafter Kim.
Regarding claim 20:
Charisoulis does not disclose the miro-LED display device of claim 19, further comprising: a power management circuit configured to manage a level of the bias voltage and the bias voltage is maintained at a value lower than a threshold voltage of each of the plurality of micro-LEDs
However, Kim discloses pixel and organic light emitting display device using the same. More particularly, Kim discloses a power management circuit (Kim Figure 6 power source supply 400) configured to manage a level of a bias voltage (Kim Figure 6 -Vbias) so that a gap voltage as a difference between a negative voltage (Kim ELVSS) and the bias voltage used to selectively drive one of a plurality of LEDs is maintained at value lower than a threshold voltage of each of the plurality of LEDs (Kim Figure 3 transistor M3 is diode connected and applied negative bias volage at node N20).
It would have been obvious to modify Krah to include power management circuit configured to manage a level of a bias voltage so that a gap voltage as a difference between a negative voltage and the bias voltage used to selectively drive one of the plurality of micro-LEDs is maintained at a value lower than a threshold voltage of each of the plurality of micro- LEDs, as claimed. Those skilled in the art would appreciate the ability to reduce a leakage current in the light emitting diode when light is not emitted (Kim [0046]).
Regarding claim 21:
Charisoulis (in view of Kim) discloses the micro-LED display device of claim 20, wherein the switch circuit includes: one or more first switched, each of the one or more first switches configured to connect each of the cathode electrodes of the first to eight micro-LEDs to the power line for the bias voltage (Charisoulis Figure 9 130 implies at least one first switch to connect Vbias to selected LEDs); and one or more second switches, each of the one or more second switches configured to connect each of the cathode electrodes to the first to eight micro-LEDs to the power line for the negative voltage (Charisoulis Figure 9 130 implies at least one first switch to connect VNEG to selected LEDs).
Claim(s) 10 – 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KRAH et al; (Publication number: US 2023/0094533 A1), hereafter Krah, in view of Kim et al; (Publication number: US 2012/0162176 A1), hereafter Kim, in view of Charisoulis et al; (Publication number: US 2023/0086380 A1), hereafter Charisoulis.
Regarding claim 10:
Krah (in view of Kim) does not disclose the micro-LED display device of claim 1, wherein each of the plurality of pixel circuits includes: a driving transistor configured to supply a power voltage in response to a gate driving voltage; a first transistor configured to constitute a current path together with the driving transistor in response to a light-emission signal; first to eight micro-LEDs, each having an anode electrode connected to the first transistor; and a switch circuit configured to selectively connect each of the cathode electrodes of the first to eight micro-LEDs to a power line for the negative voltage or the bias voltage.
However, Charisoulis discloses wherein each of the plurality of pixel circuits includes:
a driving transistor configured to supply a power voltage in response to a gate driving voltage (Charisoulis Figure 8 second transistor 106B);
a first transistor configured to constitute a current path together with the driving transistor in response to a light-emission signal (Charisoulis Figure 8 first transistor 106A);
first to eight micro-LEDs, each having an anode electrode connected to the first transistor (Charisoulis Figure see micro-driver 78 connected to subpixels 82); and
a switch circuit configured to selectively connect each of the cathode electrodes of the first to eight micro-LEDs to a power line for the negative voltage or the bias voltage (Charisoulis Figure 9 decoder 130 connects VNEG or Vbias to cathode of diode).
It would have been obvious to further modify Krah (in view of Kim) wherein each of the plurality of pixel circuits includes: a driving transistor configured to supply a power voltage in response to a gate driving voltage; a first transistor configured to constitute a current path together with the driving transistor in response to a light-emission signal; first to eight micro-LEDs, each having an anode electrode connected to the first transistor; and a switch circuit configured to selectively connect each of the cathode electrodes of the first to eight micro-LEDs to a power line for the negative voltage or the bias voltage, as claimed. Those skilled in the art would appreciate the ability to identify micro-LEDs that are malfunctioning.
Regarding claim 11:
Krah (in view of Kim and Charisoulis) discloses the micro-LED display device of claim 10, wherein the switch circuit includes: one or more first switches, each of the one or more first switches configured to connect each of the cathode electrodes of the first to eight micro-LEDs to a power line for the bias voltage (Charisoulis Figure 9 130 implies at least one first switch to connect Vbias to selected LEDs); and one or more second switches, each of the one or more second switches being configured to connect each of the cathode electrodes of the first to eight micro-LEDs to a power line for the negative voltage (Charisoulis Figure 9 130 implies at least one first switch to connect VNEG to selected LEDs).
Regarding claim 12:
Krah (in view of Kim and Charisoulis) discloses the micro-LED display device of claim 10, wherein the switch circuit is configured to apply the negative voltage to the cathode electrode of the micro-LED to emit light and to apply the bias voltage to the cathode electrode of each of the remaining micro-LEDs not to emit light (Kim Figure 3 -Vbias is applied to cathode through OLED element; Vbias voltage is more negative than ELVSS).
Allowable Subject Matter
Claims 2 – 4 and 16 – 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2 (and similarly claim 16), the prior art does not disclose the micro-LED display device of claim 1, wherein the power management circuit is configured to generate the negative voltage and provide the generated negative voltage to the display panel, and is configured to generate the bias voltage based on a negative feedback voltage fed back from the display panel and a gap setting signal corresponding to the gap voltage, as claimed.
As an example of the prior art, a bias voltage is generated by a power source (Kim ABSTRACT; Charisoulis Figure 9), but does not disclose wherein the power management circuit is configured to generate the negative voltage and provide the generated negative voltage to the display panel, and is configured to generate the bias voltage based on a negative feedback voltage fed back from the display panel and a gap setting signal corresponding to the gap voltage, as claimed.
Claims 3 and 4 depend on and 17 – 18 depend on one of claims 2 and 16, accordingly, and are therefore similarly objected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIHIR K RAYAN whose telephone number is (571)270-5719. The examiner can normally be reached Monday - Friday 9 - 5pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached at 571-272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MIHIR K RAYAN/ 11 February 2026Primary Examiner, Art Unit 2621