DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on an application filed in Germany on 2/22/2024. It is noted, however, that Applicant has not filed a certified copy of the 102024201634.9 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/14/2025 has been considered by the examiner.
Specification
The substitute specification has been received on 3/17/2025.
Claim Objections
Claims19-20 are objected to because of the following informalities:
“a control signal” in claim 19, line 5, has already been recited on lines 3-4 and the two signal should be differentiated (such as claiming a first control signal and a second control signal).
in claim 20, line 24, “wherein the DC voltage source configured” should be ‘wherein the DC voltage source is configured’.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nosaka (US 2023/0387912) in view of Ouaida (SiC Vertical JFET Pure Diode-Less Inverter Leg).
With respect to claim 11, Nosaka discloses a circuit arrangement for reducing dead time losses of an inverter, comprising: a half-bridge arrangement including a first switch (Fig. 1A Q1) and a second switch (Fig. 1A Q2); a load (Fig. 1A load connected to Vo); a control unit (Fig. 1A generates gates signals to GD1,GD2); and a driver unit (Fig. 1A GD1,GD2); wherein at least the first switch is a junction field effect transistor (Fig. 1 Q1), the load is connected to a center point (Fig. 1 node Q1-Q2) of the half-bridge arrangement, the half-bridge arrangement is configured to be connected to a DC voltage source (Fig. 1A Vin) and to provide an AC voltage to the load using a complementary control (Fig. 4 In1,In2 complementary) of the first switch and the second switch by the control unit based on a voltage of the DC voltage source, the control unit is configured to maintain a dead time (Fig. 4 time T0-T1, T2-T3) between the complementary switching of the first switch and the second switch to prevent a short circuit of the DC voltage source, and the driver unit is configured, based on a control by the control unit, to provide a gate of the first switch with a dead time voltage (Fig. 4 Vgs_Q1 during dead time) during a switch-on process and/or during a switch-off process of the first switch during the dead time, the dead time voltage being smaller than a threshold voltage (Fig. 4 Vth) of the first switch and greater (Fig. 4 vgs_Q1 before T0) than a voltage provided for blocking the first switch outside the dead time. Nosaka remains silent as to the load details. Powering inductive AC loads was well known before the effective filing date of the claimed invention.
Ouida discloses a circuit arrangement with a half-bridge (Fig. 4 Q1,Q2) wherein the load (Fig. 4 L,R) is at least partially an inductive load (Fig. 4 L). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the load is at least partially an inductive load in order to efficiently provide the power required by an inductive load, such as a motor or filtered AC device.
With respect to claim 13, Nosaka in view of Ouida make obvious the circuit arrangement according to claim 11, wherein the dead time voltage is negative, but Nosaka does not require the voltage be between −11.5 V and −19.5 V. Nevertheless, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the dead time voltage is between −11.5 V and −19.5 V, in order to minimize the power loss. See MPEP 2144.05 II. Routine Optimization. A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.”).
With respect to claim 14, Nosaka in view of Ouida make obvious the circuit arrangement according to claim 11, wherein: the second switch is a junction field effect transistor (Fig. 1A Q2), and the circuit arrangement is configured to control the second switch during the dead time in a manner corresponding (Fig. 4 Vgs_Q2 corresponds to Vgs_Q1) to the control of the first switch.
With respect to claim 15, Nosaka in view of Ouida make obvious the circuit arrangement according to claim 11, wherein the circuit arrangement is configured to dynamically adapt the dead time voltage depending on present boundary conditions (Fig. 3 Vgs dynamically varies with boundary conditions).
With respect to claim 16, Nosaka in view of Ouida make obvious the circuit arrangement according to claim 11, wherein the circuit arrangement is configured to dynamically adapt a point in time and/or a duration of a provision of the dead time voltage within the dead time depending on present boundary conditions (Fig. 3 Vgs dynamically varies with boundary conditions).
With respect to claim 17, Nosaka in view of Ouida make obvious the circuit arrangement according to claim 11, wherein the driver unit is configured to provide respective voltages (Fig. 4 Vgs_Q1, Vgs_Q2) for switching on and/or for switching off respective switches of the first and second switches and/or the dead time voltage, based on: voltage-controlled branches (Fig. 3 10) that are switched by corresponding transistors (Fig. 3 S1,S2) , and/or current-controlled branches.
With respect to claim 19, Nosaka in view of Ouida make obvious the circuit arrangement according to claim 11, wherein the driver unit is configured to: autonomously provide the dead time voltage in response to receiving a control signal (Fig. 4 In1, In2) for switching on and/or switching off from the control unit, and/or provide the dead time voltage in response to receiving a control signal (Fig. 4 In1, In2) for providing the dead time voltage from the control unit.
With respect to claim 20, Nosaka in view of Ouida make obvious electrical system, comprising: a circuit arrangement as set forth above (see claim 1 for additional details) and further comprising wherein the DC voltage source (Fig. 1A source Vin) is configured to provide the circuit arrangement with a DC voltage (Fig. 1A Vin); wherein the circuit arrangement is configured to generate the AC voltage (Fig. 1A Vo) based on the DC voltage (Fig. 1 Vo formed from Vin) and to operate the load using the AC voltage.
Allowable Subject Matter
Claims 12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 12, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the dead time voltage is a voltage that is below the threshold voltage while maintaining a required predefined tolerance as close as possible to the threshold voltage of the first switch.
With respect to claim 18, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the driver unit is configured to provide the dead time voltage based on a Zener diode.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cai (Characteristics and Application of Normally-Off SiC-JFETs in Converters Without Antiparallel Diodes) disclose switching of a JFET.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HARRY R BEHM/Primary Examiner, Art Unit 2838
Prosecution Insights