DETAILED ACTION
This office action is responsive to application 19/054,332 filed on February 14, 2025. Claims 1-12 are pending in the application.
Information Disclosure Statement
The Information Disclosure Statements (IDS) filed on 2/14/2025 and 6/04/2026 were received and have been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (figure 15) in the reply filed on June 15, 2026 is acknowledged. Applicant states that at least claims 1-20 are readable on Species 1. The Examiner respectfully disagrees. Initially, only claims 1-12 are pending in the application. Furthermore, claims 9-12 appear to be directed toward Species 2 (figure 17), as claims 9-12 recite a PMOS transistor connected to the first photoelectric conversion unit and configured to operate based on the pixel voltage. The PMOS transistor (OT’) is only present in figure 17, and therefore claims 9-12 are directed toward Species 2. As such, claims 9-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 15, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dharia et al. (US 9,973,717).
Consider claim 1, Dharia et al. teaches:
An image sensor (see figures 2 and 5), comprising:
a first pixel (i.e. a first pixel (22) of a column of pixels in figure 2, see figure 5, column 2, lines 38-44) comprising a first photoelectric conversion unit (photodiode, 102), and a first overflow transistor (transistor, 153) connected to the first photoelectric conversion unit (102, i.e. via the transfer transistor, 106, see figure 5, column 5, lines 42-49, column 6, lines 3-21);
a second pixel (i.e. a second pixel (22) of the column of pixels in figure 2 containing the first pixel, see figure 5, column 2, lines 38-44) comprising a second photoelectric conversion unit (photodiode, 102), and a second overflow transistor (transistor, 153) connected to the second photoelectric conversion unit (“Although there may be only one comparator per column, transistor 153 (which is controlled by the comparator) may be included in each pixel in the array.” column 6, lines 49-51);
a column line (column line, 32, figure 2 and 5) configured to receive a first pixel voltage obtained by converting first charges generated from the first photoelectric conversion unit (102, column 2, lines 59-63, column 3, lines 43-46), and to receive a second pixel voltage obtained by converting second charges generated from the second photoelectric conversion unit (102, column 2, lines 59-63, column 3, lines 43-46); and
a comparator (comparator, 154) configured to turn on the first overflow transistor (153) when a level of the first pixel voltage (Vpixout) is smaller than a level of a threshold voltage (anti-eclipse bias voltage, ECL_BIAS, column 5, line 57 through column 6, line 12), and to turn on the second overflow transistor (153) when the level of the second pixel voltage (Vpixout) is smaller than the level of the threshold voltage (anti-eclipse bias voltage, ECL_BIAS, column 5, line 57 through column 6, line 12). Column 6, lines 45-51 of Dharia et al. states “Additionally, although FIG. 5 only shows one pixel, it can be understood that image sensor 16 may include one comparator per column output line (and therefore one comparator per column of pixels). Although there may be only one comparator per column, transistor 153 (which is controlled by the comparator) may be included in each pixel in the array.”
Consider claim 2, and as applied to claim 1 above, Dharia et al. further teaches that the first pixel (22), the second pixel (22), and the column line (32) are disposed on a first substrate, and the comparator (154) is disposed on a second substrate below the first substrate (“Pixel array 20, control and processing circuitry 24, row control circuitry 26, and image readout circuitry 28 may be formed on a substrate 23. If desired, some or all of the components of image sensor 16 may instead be formed on substrates other than substrate 23, which may be connected to substrate 23, for instance, through wire bonding or flip-chip bonding.” column 2, lines 48-54).
Consider claim 3, and as applied to claim 1 above, Dharia et al. further teaches that each of the first pixel (22) and the second pixel (22) further comprises a first transistor (e.g. reset transistor, 108, figure 5) connected to an output end of the comparator (154, i.e. via transistor 153, see figure 5) and a second transistor (e.g. row select transistor, 112, figure 5) connected to an input end of the comparator (see figure 5, column 5, lines 47-56).
Consider claim 4, and as applied to claim 1 above, Dharia et al. further teaches that the first pixel (22) is configured to receive a first selection signal (SEL) which selects the first pixel (see column 3, lines 43-46), the second pixel (22) is configured to receive a second selection signal (SEL) which selects the second pixel (see column 3, lines 43-46), and the first comparator (154) is configured to operate when the first selection signal (SEL) or the second selection signal (SEL) has a logic high level (see figure 6, column 6, line 52 through column 7, line 34).
Consider claim 5, and as applied to claim 1 above, Dharia et al. further teaches that the first overflow transistor (153) is configured to drain the first charges of the first photoelectric conversion unit (i.e. by connecting the floating diffusion region (104) on which the first charges of the photoelectric conversion unit (102) are stored according to the output of the comparator (154), see column 6, lines 13-29), and the second overflow transistor (153) is configured to drain the second charges of the second photoelectric conversion unit (i.e. by connecting the floating diffusion region (104) on which the second charges of the photoelectric conversion unit (102) are stored according to the output of the comparator (154), see column 6, lines 13-29).
Consider claim 6, and as applied to claim 5 above, Dharia et al. further teaches that the level of the first pixel voltage when the first charges of the first photoelectric conversion unit are drained is greater than the level of the threshold voltage (“If Vpixout drops below ECL_BIAS, the output of comparator 154 will assert transistor 153, coupling floating diffusion region 104 to power supply terminal 160. This will raise the charge at floating diffusion region 104 to approximately the bias voltage provided by power supply terminal 160. Vpixout will increase accordingly. If Vpixout increases higher than ECL_BIAS, transistor 153 will be deasserted and the floating diffusion region will no longer be coupled to power supply terminal 160.” column 6, lines 23-32), and the level of the second pixel voltage when the second charges of the second photoelectric conversion unit are drained is greater than the level of the threshold voltage (“If Vpixout drops below ECL_BIAS, the output of comparator 154 will assert transistor 153, coupling floating diffusion region 104 to power supply terminal 160. This will raise the charge at floating diffusion region 104 to approximately the bias voltage provided by power supply terminal 160. Vpixout will increase accordingly. If Vpixout increases higher than ECL_BIAS, transistor 153 will be deasserted and the floating diffusion region will no longer be coupled to power supply terminal 160.” column 6, lines 23-32).
Consider claim 7, and as applied to claim 1 above, Dharia et al. further teaches that the column line (32) is connected to both the first and second pixels (see column 2, lines 59-67), and extends in a first direction (i.e. a vertical direction in figures 2 and 5), and the first pixel (22) is separated from the second pixel (22) in the first direction (i.e. in the vertical, column direction in figure 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dharia et al. (US 9,973,717) in view of Lee et al. (US 10,714,517).
Consider claim 8, and as applied to claim 1 above, Dharia et al. further teaches that the first pixel further comprises a third photoelectric conversion unit spaced apart from the first photoelectric conversion unit, the second pixel further comprises a fourth photoelectric conversion unit spaced apart from the second photoelectric conversion unit and an area of the first photoelectric conversion unit is greater than an area of the third photoelectric conversion unit and an area of the second photoelectric conversion unit is greater than an area of the fourth photoelectric conversion unit.
Lee et al. similarly teaches a first unit pixel (figure 18) comprising a first photoelectric conversion unit (PD1) configured to generate first charges in response to a first incident light (column 5, lines 61-65, column 6, lines 47-49), and a second unit pixel (i.e. of a column of the pixel array (11) in figure 1 containing the first pixel unit, see figure 18) comprising a second photoelectric conversion unit (PD1) configured to generate second charges in response to a second incident light (column 5, lines 61-65, column 6, lines 47-49)
However, Lee et al. additionally teaches that the first pixel (figure 18) further comprises a third photoelectric conversion unit (PD2) spaced apart from the first photoelectric conversion unit (PD1), the second pixel (figure 18) further comprises a fourth photoelectric conversion unit (PD2) spaced apart from the second photoelectric conversion unit (PD1) and an area of the first photoelectric conversion unit (PD1) is greater than an area of the third photoelectric conversion unit (PD2, see figure 4, column 6, lines 5-30) and an area of the second photoelectric conversion unit (PD1) is greater than an area of the fourth photoelectric conversion unit (PD2, see figure 4, column 6, lines 5-30).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first and second pixels taught by Dharia et al. each include two photoelectric conversion units which are respectively greater and smaller in area as taught by Lee et al. for the benefit of enabling a signal lamp to be accurately detected while preventing erroneous sensing of light from the signal lamp (Lee et al., column 6, lines 13-30).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chu et al. (US 2020/0396401) teaches a pixel configuration (figure 8B) with two pixels (110c-r1, 110c-r2), two photodiodes (112), and a single comparator (122) connected to two reset transistors (116).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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