Prosecution Insights
Last updated: July 17, 2026
Application No. 19/054,460

SYSTEM POWER MANAGEMENT IN MULTI-PORT I/O HYBRID SYSTEMS

Non-Final OA §102§103
Filed
Feb 14, 2025
Priority
Aug 18, 2020 — continuation of 12/228,992
Examiner
PATEL, NIMESH G
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
560 granted / 726 resolved
+22.1% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
15 currently pending
Career history
746
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
66.1%
+26.1% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 726 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,228,992. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims 1-20 fall entirely within the scope of claims 1-18 of U.S. Patent No. 12,228,992. The elements in claims 1-20 of the current application and the corresponding elements in claims 1-18 of U.S. Patent No. 12,228,992 are substantially the same and therefore the instant claims 1-20 are obvious over claims 1-18 of U.S. Patent No. 12,228,992. For example, claim 1 of U.S. Patent No. 12,228,992 teaches claim 1 of the present application. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5-10 and 13-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goel(US 20190332558). Regarding claims 1 and 10, Goel discloses an apparatus and method comprising: a host controller(Figure 2A, 202) to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect(Paragraph 38, the basic tunneling protocol may be Universal Serial Bus (USB) 4.0) for a plurality of devices(Figure 2A, 222, 242), wherein the host controller is to: monitor control plane messages on the interconnect; detect, in the control plane messages, a power state change command for a device coupled to the interconnect(Paragraph 52, Such detection may include detecting power level commands), wherein the devices utilizes a tunneled protocol on the interconnect(Paragraph 38, tunnels the DISPLAYPORT protocol to both displays 104 and 106 such that both displays 104 and 106 are synchronized); and modify power distribution for one or more other devices of the interconnect based on detecting the power state change command(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 5, Goel discloses apparatus of claim 1, wherein the power state change command is a low power command for a power sink device, and the host controller is to redistribute power to one or more other devices coupled to the interconnect based on detection of the low power command(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 6, Goel discloses apparatus of claim 1, wherein the power state change command is a low power command for a power source device, and the host controller is to cause one or more other devices coupled to the interconnect to transition into a low power mode based on detection of the low power command(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 7, Goel discloses apparatus of claim 6, wherein the host controller is to cause one or more other devices coupled to the interconnect to transition into a low power mode by renegotiating device power policies for the devices(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 8, Goel discloses apparatus of claim 1, wherein the tunneled protocol is one of a DisplayPort-based protocol and a Peripheral Component Interconnect Express (PCIe)-based protocol(Paragraph 38, native protocols may include, but are not limited to, a USB protocol, high definition multimedia interface (HDMI), DISPLAYPORT, Peripheral Component Interconnect (PCI) and variations such as PCI express (PCIE)). Regarding claim 9, Goel discloses apparatus of claim 1, wherein the USB-based protocol is a USB4 protocol(Paragraph 38, the basic tunneling protocol may be Universal Serial Bus (USB) 4.0). Regarding claim 13, Goel discloses method of claim 10, further comprising determining that the device is a power sink, wherein modifying power distribution comprises redistributing power to one or more devices coupled to the USB-based interconnect(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 14, Goel discloses method of claim 10, further comprising determining that the device is a power source, wherein modifying power distribution comprises renegotiating a device power policy for one or more other devices coupled to the USB-based interconnect(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 15, Goel discloses method of claim 10, wherein USB-based interconnect implements a USB4 protocol, and the tunneled protocol is one of a DisplayPort-based protocol and a Peripheral Component Interconnect Express (PCIe)-based protocol(Paragraph 38, native protocols may include, but are not limited to, a USB protocol, high definition multimedia interface (HDMI), DISPLAYPORT, Peripheral Component Interconnect (PCI) and variations such as PCI express (PCIE)). Regarding claim 16, Goel discloses a system comprising: a first device(Figure 2A, 202); a second device(Figure 2A, 222) coupled to the first device via a Universal Serial Bus (USB)-based interconnect; a third device(Figure 2A, 242) coupled to the first and second devices via the USB-based interconnect, wherein the third device communicates with the first and second devices on the USB-based interconnect using a tunneled protocol(Paragraph 38, USB 4.0 tunnels the DISPLAYPORT protocol to both displays 104 and 106; wherein the first device comprises a host controller to implement a connection manager (CM) and a device policy manager (DPM), the CM to: detect a low power command for the second device, the low power command to cause the second device to transition to a low power mode; and provide an indication of the low power command to the DPM; and wherein the DPM is to manage power distribution policies for the devices based on the indication(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 17, Goel discloses system of claim 16, wherein the CM is to provide an indication of the low power command to the DPM using an Operating System Power Policy Manager (OSPPM)(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 18, Goel discloses system of claim 16, wherein the DPM is to redistribute power to the second device based on the indication(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 19, Goel discloses system of claim 16, wherein the DPM is to modify a device power policy for the second device based on the indication(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system. For example, one downstream display may enter a deep sleep mode while downstream speakers continue to play music). Regarding claim 20, Goel discloses system of claim 16, wherein the USB-based interconnect implements a USB4 protocol, and the tunneled protocol is one of a DisplayPort-based protocol and a Peripheral Component Interconnect Express (PCIe)-based protocol(Paragraph 38, the basic tunneling protocol may be Universal Serial Bus (USB) 4.0, native protocols may include, but are not limited to, a USB protocol, high definition multimedia interface (HDMI), DISPLAYPORT, Peripheral Component Interconnect (PCI) and variations such as PCI express (PCIE)). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-4 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goel and Regupathy(US 2019/0138078). Regarding claims 2 and 11, Goel discloses the apparatus of claim 1, wherein the host controller is to implement a connection manager (CM) to monitor the control plane messages(Paragraph 33, By managing power for lanes in this fashion, individual downstream devices may be managed independently of one another to provide a system-wide optimized power management system), but does not specifically disclose the CM is to generate an interrupt based on detecting power state change commands. However, Regupathy discloses detecting an interrupt indicating entry or exit of low power states. It would have been obvious to one of ordinary skill in the art at the time of filing to combine the teachings of Goel and Regupathy to have the CM generate an interrupt based on detecting power state change commands. The motivation to do so would be to alert of power state changes. Regarding claims 3 and 12, Goel and Regupathy disclose the apparatus of claim 2, wherein the CM is to generate the interrupt by setting one or more bits of a status register in the host controller(Regupathy: Paragraph 25). Regarding claim 4, Goel and Regupathy disclose the apparatus of claim 2, wherein host controller is further to implement a device policy manager (DPM) to manage power delivery policies for devices coupled to the interconnect, and the CM is to provide an indication of the power state change command to the DPM using an Operating System Power Policy Manager (OSPPM)(Paragraph 25, USB controller provides the low power state information to the device policy manager (DPM) to allow the DPM to change a power requirement for a device of the plurality of devices or renegotiating a power contract with the device). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached Monday-Friday, 8:15-4:15. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMESH G PATEL/ Primary Examiner, Art Unit 2187
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Prosecution Timeline

Feb 14, 2025
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
84%
With Interview (+7.4%)
2y 10m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 726 resolved cases by this examiner. Grant probability derived from career allowance rate.

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