DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ferguson et al. (US 5,789,974) in view of Lin et al. (US 5,248,907).
Consider claims 1, 9 and 17:
Ferguson discloses an electronic device (see Fig. 2 and col. 5, lines 40-45, where Ferguson describes an offset calibration circuit 36), comprising:
a receiver (see Fig. 2 and col. 6, lines 1-20, where Ferguson describes that the offset calibration circuit 36 includes a Logic Circuit 42 which receives logic signals at input 56); and
a transmitter coupled to the receiver via a cable, the transmitter comprising an amplifier (see Fig. 2 and col. 6, lines 1-20, where Ferguson describes an Amplifier 40 which sends the logic signals to the Logic Circuit 42 through a wire), and
offset tracking circuitry coupled to the amplifier (see Fig. 2 and col. 6, lines 1-2, where Ferguson describes an Offset Compensation Circuit 38 which is connected to the Amplifier 40),
the offset tracking circuitry configured to compensate for a voltage offset between the receiver and transmitter (see Fig. 2 and col. 6, lines 1-21, where Ferguson describes that the Offset Compensation Circuit 38 is configured to compensate for a direct current (DC) offset of the Amplifier 40) based on a ground bounce associated with the cable (see Fig. 2 and col. 7, lines 1-15, where Ferguson describes that the Offset Compensation Circuit 38 applies voltages V+ and V- to the Amplifier 40 to compensate for the DC-offset, the voltage V- is switched to ground GND through switch S17 during the DC-offset compensation; see Fig. 2 and col. 6, lines 45-60, where Ferguson describes that the voltage V- is associated with the wire on which the Amplifier 40 sends the logic signals to the Logic Circuit 42).
As discussed above, Ferguson discloses a switch S17 which switches between a voltage and a ground GND (see Fig. 2 and col. 7, lines 1-15). However, Ferguson does not explicitly disclose: the switch S17 creates “ground bounce”.
Lin teaches: a “ground bounce” is created when switching from a voltage to ground (see col. 1, lines 63-68, where Lin describes that a “ground bounce” occurs when a circuit switches its output node from high voltage level to ground).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the switch S17 generates “ground bounce”, as taught by Lin to modify the method of Ferguson in order to improve output signal in a MOS output buffer, as discussed by Lin (see col. 2, lines 59-60).
Consider claim 2:
Ferguson in view of Lin discloses the electronic device of claim 1 above. Ferguson discloses: the ground bounce is generated by a ground resistance of the cable (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the switch S17 is connected to a resistor 24B).
Consider claim 7:
Ferguson in view of Lin discloses the electronic device of claim 1 above. Ferguson discloses: the amplifier comprises an input resistor and a feedback resistor, the amplifier configured to receive an input value based on a first resistance of the input resistor and a second resistance of the feedback resistor (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 receives input signals through an input resistor 24B and a feedback resistor 24A).
Consider claim 8:
Ferguson in view of Lin discloses the electronic device of claim 7 above. Ferguson discloses: the input value is indicative of the first resistance of the input resistor divided by a sum of the first resistance of the input resistor and the second resistance of the feedback resistor (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that input signals of the Amplifier 40 is determined by ratio of resistances of resistor 24A and 24B).
Consider claim 10:
Ferguson in view of Lin discloses the transmitter of claim 9 above. Ferguson discloses: the transmitter is coupled to a receiver via the electrical ground (see Fig. 2 and col. 7, lines 1-15, where Ferguson describes that when switch S17 is closed, voltage V- is ground GND, and voltage V- is connected to the Logic Circuit 42 through the Amplifier 40).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ferguson et al. (US 5,789,974) in view of Lin et al. (US 5,248,907), as applied to claim 1 above, and further in view of Liang et al. (US 11,243,551 B1).
Consider claim 3:
Ferguson in view of Lin discloses the electronic device of claim 1 above. Ferguson discloses: the amplifier comprises a first positive input (see Fig. 2 and col. 6, lines 1-10, where Ferguson describes that the amplifier 40 includes a first positive input 54).
Ferguson does not specifically disclose: the amplifier comprises a first positive input and a second positive input.
Liang teaches: an amplifier comprises a first positive input and a second positive input (see Fig. 4 and col. 7, lines 17-29, where Liang describes a compensation circuit in which an amplifier 460 includes a first positive input and a second positive input).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the amplifier comprises a first positive input and a second positive input, as taught by Liang to modify the method of Ferguson in order to provide a dynamic voltage compensation, as discussed by Liang (see col. 1, lines 24-25).
Claims 4, 5 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ferguson et al. (US 5,789,974) in view of Lin et al. (US 5,248,907), as applied to claims 1 and 17 above, and further in view of Kim et al. (US 6,738,417 B1).
Consider claims 4 and 18:
Ferguson in view of Lin discloses the invention of claims 1 and 17 above. Ferguson and Lin do not specifically disclose: the receiver comprises a first unit gain buffer, the transmitter comprises a second unit gain buffer, and the first unit gain buffer is coupled to the second unit gain buffer via a connector.
Kim teaches: a receiver comprises a first unit gain buffer, a transmitter comprises a second unit gain buffer, and the first unit gain buffer is coupled to the second unit gain buffer via a connector (see Fig. 6 and col. 4, lines 12-31, where Kim describes a receiver RX 22 that includes a second unit gain buffer 26, a transmitter TX 21 that includes a first unit gain buffer 23, and the second unit gain buffer 26 is connected to the first unit gain buffer 23 through a cable 27).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the receiver comprises a first unit gain buffer, the transmitter comprises a second unit gain buffer, and the first unit gain buffer is coupled to the second unit gain buffer via a connector, as taught by Kim to modify the method of Ferguson and Lin in order to provide a bidirectional data transfer, as discussed by Kim (see col. 1, lines 40-45).
Consider claim 5:
Ferguson in view of Lin and Kim discloses the electronic device of claim 4 above. Ferguson and Lin do not specifically disclose: the receiver comprises a voltage source coupled to a positive input of the first unit gain buffer, the voltage source configured to generate a reference voltage signal.
Kim teaches: a receiver comprises a voltage source coupled to a positive input of a first unit gain buffer, the voltage source configured to generate a reference voltage signal (see Fig. 6 and col. 4, lines 25-31, where Kim describes that the receiver RX 22 includes voltage at node B which contains signal BackTData that is connected to input of second unit gain buffer 26, the node B generates a reference clock RxClk).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the receiver comprises a voltage source coupled to a positive input of the first unit gain buffer, the voltage source configured to generate a reference voltage signal, as taught by Kim to modify the method of Ferguson and Lin in order to provide a bidirectional data transfer, as discussed by Kim (see col. 1, lines 40-45).
Consider claim 19:
Ferguson in view of Lin and Kim discloses the transceiver of claim 18 above. Ferguson and Lin do not specifically disclose: the amplifier comprises a first positive input configured to receive the reference voltage signal via the first unit gain buffer and the second unit gain buffer.
Kim teaches: an amplifier comprises a first positive input configured to receive the reference voltage signal via the first unit gain buffer and the second unit gain buffer (see Fig. 6 and col. 4, lines 11-31, where Kim describes an amplifier 25 which includes a positive input configured to receive BackTData from the second unit gain buffer 26 through the node B which also receives signal from the first unit gain buffer 23),
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the amplifier comprises a first positive input configured to receive the reference voltage signal via the first unit gain buffer and the second unit gain buffer, as taught by Kim to modify the method of Ferguson and Lin in order to provide a bidirectional data transfer, as discussed by Kim (see col. 1, lines 40-45).
Consider claim 20:
Ferguson in view of Lin and Kim discloses the transceiver of claim 19 above. Ferguson discloses: the amplifier comprises an input resistor, a feedback resistor, and a second positive input coupled to the input resistor and the feedback resistor (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 receives input signals through an input resistor 24B and a feedback resistor 24A).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ferguson et al. (US 5,789,974) in view of Lin et al. (US 5,248,907) and Kim et al. (US 6,738,417 B1), as applied to claim 4 above, and further in view of Prasad et al. (US 2004/0210801 A1).
Consider claim 6:
Ferguson in view of Lin and Kim discloses the electronic device of claim 4 above. Ferguson does not specifically disclose: the receiver comprises a first high pass filter coupled to the first unit gain buffer, and the transmitter comprises a second high pass filter coupled to the second unit gain buffer.
Prasad teaches: a first high pass filter coupled to a first unit gain buffer (see Fig. 3 and paragraph 0025, where Prasad describes a capacitor 201a which is connected to a unit gain buffer 301a; see paragraph 0022, where Prasad describes that the capacitor 201a acts as high-pass filter).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the receiver comprises a first high pass filter coupled to the first unit gain buffer, and the transmitter comprises a second high pass filter coupled to the second unit gain buffer, as taught by Prasad to modify the method of Ferguson in order to attenuate very low frequency components, as discussed by Prasad (see paragraph 0022).
Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ferguson et al. (US 5,789,974) in view of Lin et al. (US 5,248,907), as applied to claim 10 above, and further in view of Yamaguchi (US 2002/0050839 A1).
Consider claim 11:
Ferguson in view of Lin discloses the transmitter of claim 10 above. Ferguson and Lin do not specifically disclose: the ground bounce comprises a ground potential mismatch between the transmitter and the receiver.
Yamaguchi teaches: a ground potential mismatch between a transmitter and a receiver (see Fig. 2 and paragraph 0042, where Yamaguchi describes a transmitter circuit 20 and receiver circuit 10 connected by transmission lines 17 and 18, the ground potential of the receiver circuit is sometimes different from the ground potential of the transmitter circuit).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the ground bounce comprises a ground potential mismatch between the transmitter and the receiver, as taught by Yamaguchi to modify the method of Ferguson and Lin in order to include noise generated during a long-distance signal transmission, as discussed by Yamaguchi (see paragraph 0042).
Consider claim 12:
Ferguson in view of Lin and Yamaguchi discloses the transmitter of claim 11 above. Ferguson discloses: the amplifier comprises a first set of amplification stages coupled to the offset tracker (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to include two opened switches S17 and S18, in which the Amplifier 40 is receiving voltage V+ from the Offset Compensation Circuit 38) and a second set of amplification stages configured to receive a reference voltage signal from the receiver (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to include one opened switch S12, in which the Amplifier 40 is configured as a comparator; see Fig. 2 and col. 7, lines 1-15, where Ferguson describes that when switch S12 is open, the Amplifier 40 receives a reference voltage from ground GND controlled by the Logic Circuit 42).
Consider claim 13:
Ferguson in view of Lin and Yamaguchi discloses the transmitter of claim 11 above. Ferguson discloses: the amplifier comprises a multiplexer, a first set of amplification stages, and a second set of amplification stages (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to select either opening switches S17 and S18, or opening switch S12).
Consider claim 14:
Ferguson in view of Lin and Yamaguchi discloses the transmitter of claim 13 above. Ferguson discloses: the multiplexer is configured to enable the first set of amplification stages to receive a reference voltage signal from the receiver (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to include one opened switch S12, in which the Amplifier 40 is configured as a comparator; see Fig. 2 and col. 7, lines 1-15, where Ferguson describes that when switch S12 is open, the Amplifier 40 receives a reference voltage from ground GND controlled by the Logic Circuit 42) and couple the second set of amplification stages to the offset tracker (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to include two opened switches S17 and S18, in which the Amplifier 40 is receiving voltage V+ from the Offset Compensation Circuit 38).
Consider claim 15:
Ferguson in view of Lin and Yamaguchi discloses the transmitter of claim 13 above. Ferguson discloses: the first set of amplification stages comprises a first number of amplification stages (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to include two opened switches S17 and S18), the second set of amplification stages comprises a second number of amplification stages, and the first number of amplification stages is greater than the second number of amplification stages (see Fig. 2 and col. 5, lines 40-63, where Ferguson describes that the Amplifier 40 may be configured to include one opened switch S12).
Consider claim 16:
Ferguson in view of Lin and Yamaguchi discloses the transmitter of claim 13 above. Ferguson discloses: an output of the multiplexer is based on a control signal used to program an output of the offset tracker to compensate for the voltage offset (see Fig. 2, col. 5, lines 64-67 and col.6, lines 1-21, where Ferguson describes that output of the Offset Compensation Circuit 38 is controlled by Logic Circuit 42).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIHONG YU whose telephone number is (571)270-5147. The examiner can normally be reached 10:00 am-6:00 pm EST Monday-Friday.
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/LIHONG YU/Primary Examiner, Art Unit 2631
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