DETAILED ACTION
The instant application having Application No. 19/054,539 has a total of 20 claims pending in the application, there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
As required by M.P.E.P. ' 201.14(c), acknowledgment is made of applicant's claim for priority based on an application KR10-2024-0084650 filed in REPUBLIC OF KOREA
06/27/2024.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant's drawings submitted 2/14/2025 are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 2/14/2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9 and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 2022/0317918) in view of Nag et al (US 2024/0012757).
Regarding Claim 1, Golov teaches an electronic system configured to be mounted at a vehicle, comprising:
a first sensor device configured to detect first environmental information of the vehicle and to generate first sensor data based on the first environmental information (first sensor device corresponding to Sensor A 121 of Fig. 3, which generates a packet/first sensor data, Paragraphs 0037-0039, and “sensors 139 can be configured primarily to monitor the environment of the vehicle,” Paragraph 0033);
an integrated memory device (memory sub-system 310 of Fig. 7) including a memory interface circuit (see interface with host 320, Paragraph 0092), an integrated controller (controller 314 of Fig. 7, Paragraph 0099), a first volatile memory device (volatile memory 103 of Fig. 3, which is part of data recorder 101 of Fig. 1, and “at least a portion of the data recorder 101 can be implemented as a memory sub-system” as shown on Fig. 7), and a non-volatile memory device (non-volatile memory 109 of Fig. 3, which is part of data recorder 101 of Fig. 1, and “at least a portion of the data recorder 101 can be implemented as a memory sub-system” as shown on Fig. 7); and
a host device including a host interface circuit (host system 320 of Fig. 7, with the interface described on Paragraph 0092), wherein the integrated controller is configured to:
obtain the first sensor data from the first sensor device (see Fig. 1, where data from sensors is obtained by the Sensor Data Manager 112),
store the first sensor data in the first volatile memory device as buffered first sensor data (“outputs of the sensors 139 to the data recorder 101 are initially buffered in the volatile memory 103,” Paragraph 0036),
store the buffered first sensor data in the non-volatile memory device (“The sensor data slices 150 are flushed into the buffer region 111” of the non-volatile memory device, Paragraph 0036), and
provide the buffered first sensor data to the host device through the memory interface circuit and the host interface circuit (“The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system,” Paragraph 0086).
However, Golov does not explicitly teach an integrated memory device including a compute express link (CXL) memory interface circuit or a host device including a CXL host interface circuit.
Nag teaches an integrated memory device including a compute express link (CXL) memory interface circuit and a host device including a CXL host interface circuit (“the memory device is a Compute Express Link (CXL) device that communicates with the CPU(s) in accordance with the Compute Express Link (CXL) standard (e.g., CXL 2.0), which allows interconnect to provide high-bandwidth, low-latency connectivity between a host processor (e.g., CPU of a vehicle) and devices (e.g., memory device having an offloading engine,” Paragraph 0036).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the CXL interface of Nag in the cited prior art in order “to provide high-bandwidth, low-latency connectivity between a host processor (e.g., CPU of a vehicle and devices” (Paragraph 0036 of Nag).
Regarding Claim 2, the cited prior art teaches the electronic system of claim 1, wherein the CXL memory interface circuit and the CXL host interface circuit are configured to communicate based on a peripheral component interconnect express (PCIe)-based non-coherent input/output protocol, and based on a memory access protocol supporting memory access (“use of the CXL device enables coherency and memory semantics on top of PCI Express® (PCIe®) 5.0 based I/O semantics,” Paragraph 0036 of Nag).
Regarding Claim 3, the cited prior art teaches the electronic system of claim 1, further comprising second to M-th sensor devices (sensors such as Sensor B 123 and Sensor C 125 of Fig. 3),
wherein the second to M-th sensor devices are configured to:
detect second to M-th environmental information of the vehicle, respectively (sensors 139 can be configured primarily to monitor the environment of the vehicle,” Paragraph 0033); and
generate second to M-th sensor data, respectively, based on the second to M-th environmental information (see Fig. 1, where data from sensors is obtained by the Sensor Data Manager 112, and therefore sensor data must be generated), and
wherein the integrated controller is further configured to:
obtain the second to N-th sensor data, among the second to M-th sensor data, from the second to N-th sensor devices, among the second to M-th sensor devices, respectively, wherein "N" is a natural number greater than 2, and "M" is a natural number greater than "N" (see Fig. 1, where data from sensors is obtained by the Sensor Data Manager 112);
store the second to N-th sensor data in the first volatile memory device as buffered second to N-th sensor data (“outputs of the sensors 139 to the data recorder 101 are initially buffered in the volatile memory 103,” Paragraph 0036);
store the buffered second to N-th sensor data in the non-volatile memory device (“The sensor data slices 150 are flushed into the buffer region 111” of the non-volatile memory device, Paragraph 0036);
and provide the buffered second to N-th sensor data to the host device (“The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system,” Paragraph 0086) through the CXL memory interface circuit and the CXL host interface circuit (“the memory device is a Compute Express Link (CXL) device that communicates with the CPU(s) in accordance with the Compute Express Link (CXL) standard (e.g., CXL 2.0), which allows interconnect to provide high-bandwidth, low-latency connectivity between a host processor (e.g., CPU of a vehicle) and devices (e.g., memory device having an offloading engine,” Paragraph 0036 of Nag).
Regarding Claim 4, the cited prior art teaches the electronic system of claim 3, wherein each of the first to M-th sensor devices includes at least one of a radio detection and ranging (RADAR) device, a light detection and ranging (LiDAR) device, or a camera (Paragraph 0032).
Regarding Claim 9, the cited prior art teaches the electronic system of claim 1, wherein the integrated controller is further configured to:
read, as read first sensor data, the buffered first sensor data from the first volatile memory device in response to the first sensor data being stored in the first volatile memory device (“The sensor data slices 150 are flushed into the buffer region 111” of the non-volatile memory device, Paragraph 0036, therefore sensor data is read from volatile memory and written to non-volatile memory); allocate a first physical address to the read first sensor data, the first physical address being associated with the non-volatile memory device; and store the read first sensor data in a storage area of the non-volatile memory device corresponding to the first physical address (“a write command can be sent from the processor of the data recorder 101 to the solid state drive (SSD) according to a non-volatile memory express (NVMe) protocol using the LBA address to store a sensor data slice (e.g., 161) into a slot in the cyclic buffer region 111,” Paragraph 0081, and as the logical addresses are translated into physical addresses, Paragraph 0102, a physical address is obviously allocated for the first sensor data).
Claim 12 is the method corresponding to the electronic system of claim 1, and is rejected under similar rationale.
Claim 13 is the method corresponding to the electronic system of claim 2, and is rejected under similar rationale.
Claim 14 is the method corresponding to the electronic system of claim 9, and is rejected under similar rationale.
Regarding Claim 15, the cited prior art teaches the method of claim 12, wherein the electronic
system further includes a second sensor device (see sensor B 123 of Fig. 3), and wherein the method further comprises:
detecting, by the second sensor device, second environmental information of the vehicle (sensors 139 can be configured primarily to monitor the environment of the vehicle,” Paragraph 0033); generating, by the second sensor device, second sensor data based on the second environmental information (see Fig. 1, where data from sensors is obtained by the Sensor Data Manager 112, and therefore sensor data must be generated); obtaining, by the host device, the second sensor data (“The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system,” Paragraph 0086).
However, Golov does not explicitly teach providing, by the host device, the second sensor data to the integrated memory device through the CXL host interface circuit and the CXL memory interface circuit.
Nag teaches providing, by the host device (CXL device 202), the second sensor data to an integrated memory device through the CXL host interface circuit and the CXL memory interface circuit (sensor data is provided from a host to memory device/CXL cache 208 through a CXL interface as shown on Fig. 2, Paragraph 0080).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the providing of Nag in the cited prior art in order to allow a vehicle to automatically perform one or more functions (Paragraph 0080).
Regarding Claim 16, the cited prior art teaches the method of claim 15, further comprising: allocating, by an integrated controller of the integrated memory device, a second physical address to the second sensor data, the second physical address being associated with the non- volatile memory device; and storing, by the integrated controller, the second sensor data in a storage area of the non- volatile memory device corresponding to the second physical address (“a write command can be sent from the processor of the data recorder 101 to the solid state drive (SSD) according to a non-volatile memory express (NVMe) protocol using the LBA address to store a sensor data slice (e.g., 161) into a slot in the cyclic buffer region 111,” Paragraph 0081, and as the logical addresses are translated into physical addresses, Paragraph 0102, a physical address is obviously allocated for the second sensor data).
Claim 17 is the integrated memory device corresponding to the electronic system of claim 1, and is rejected under similar rationale.
Claim 18 is the integrated memory device corresponding to the electronic system of claim 2, and is rejected under similar rationale.
Claim 19 is the integrated memory device corresponding to the electronic system of claim 9, and is rejected under similar rationale.
Regarding Claim 20, the cited prior art teaches of Golov teaches the integrated memory device of claim 17, allocate, to the second sensor data, a second physical address that is associated with the non-volatile memory device; and store the second sensor data in a storage area of the non-volatile memory device corresponding to the second physical address (“a write command can be sent from the processor of the data recorder 101 to the solid state drive (SSD) according to a non-volatile memory express (NVMe) protocol using the LBA address to store a sensor data slice (e.g., 161) into a slot in the cyclic buffer region 111,” Paragraph 0081, and as the logical addresses are translated into physical addresses, Paragraph 0102, a physical address is obviously allocated for the second sensor data).
However, Golov does not explicitly teach wherein the integrated controller is further configured to: receive second sensor data from the host device through the CXL memory interface circuit.
Nag teaches to receive second sensor data from the host device through the CXL memory interface circuit (sensor data is provided from a host to memory device/CXL cache 208 through a CXL interface as shown on Fig. 2, Paragraph 0080).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the providing of Nag in the cited prior art in order to allow a vehicle to automatically perform one or more functions (Paragraph 0080).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 2022/0317918) in view of Nag et al (US 2024/0012757) and Watts et al (US 11,987,266).
Regarding Claim 5, the cited prior art teaches the electronic system of claim 3, further comprising a second volatile memory device (buffer B 133 of Fig. 3)
However, the cited prior art does not explicitly teach a second volatile memory device configured to communicate with the host device through a memory interface circuit, wherein the host device is configured to:obtain the (N+1)-th to M-th sensor data, among the second to M-th sensor data, from the (N+1)-th to M-th sensor devices. among the second to M-th sensor devices; and store the (N+1)-th to M-th sensor data in the second volatile memory device.
Watts teaches a second volatile memory device configured to communicate with the host device through a memory interface circuit, wherein the host device is configured to:obtain (N+1)-th to M-th sensor data, among the second to M-th sensor data, from the (N+1)-th to M-th sensor devices. among the second to M-th sensor devices; andstore the (N+1)-th to M-th sensor data in the second volatile memory device ((N+1)-th to M-th sensor devices corresponding to data from a particular zone, each having its own memory for storage corresponding to Zone ECU 110(1)-110(4) of Fig. 3, also see C6 L61-C7 L15).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the zones of Watts in the cited prior art in order to reduce load on individual memory devices.
Regarding Claim 6, the cited prior art teaches the electronic system of claim 5, wherein the memory interface circuit is based on a double data rate (DDR) protocol (a double data rate (DDR) memory bus interface, Paragraph 0092 of Golov), and wherein the second volatile memory device is a dynamic random access memory (DRAM) (Paragraph 0023 of Golov).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 2022/0317918) in view of Nag et al (US 2024/0012757) and Zhou et al (US 2026/0046452).
Regarding Claim 10, the cited prior art teaches the electronic system of claim 1, but does not explicitly teach wherein the non-volatile memory device is detachable from other components of the integrated memory device.
Zhou teaches wherein a non-volatile memory device is detachable (Paragraphs 0225-0226).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the detachable non-volatile memory device of Zhou in the cited prior art in order to easily replace the non-volatile memory if necessary.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Golov (US 2022/0317918) in view of Nag et al (US 2024/0012757) and Fader et al (US 2021/0360090).
Regarding Claim 11, the cited prior art teaches the electronic system of claim 1, but does not explicitly teach wherein the integrated memory device is configured to receive the first sensor data through a camera serial interface (CSI) circuit.
Fader teaches a camera serial interface (Paragraph 0002).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the camera serial interface (CSI) circuit of Fader in the cited prior art in order to easily communicate between a memory device and sensor.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Kale et al (US 2024/0184456) teaches MANAGEMENT OF VEHICLE SYSTEM INFORMATION USING A DEEP LEARNING DEVICE.
Wu (US 2024/0176536) teaches PARTITIONS WITHIN BUFFER MEMORY.
CLOSING COMMENTS
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
SUBJECT MATTER CONSIDERED ALLOWABLE
Regarding Claim 7, the cited prior art teaches the electronic system of claim 5, but does not teach wherein the integrated controller includes a non- volatile memory express (NVMe) protocol processor, and wherein the NVMe protocol processor is configured to: receive at least one access request from the host device through the CXL memory interface circuit, the at least one access request corresponding to the (N+1)-th to M-th sensor data; and convert the at least one access request into at least one storage access request complying with a storage protocol that supports access to the non-volatile memory device, wherein the integrated controller is configured to store the (N+1)-th to M-th sensor data in the non-volatile memory device based on the at least one storage access request.
Though the prior art teaches transferring data from data from volatile to non-volatile memory (Paragraph 0036 of Golov), this is not done in response to at least one access request from the host device through the CXL memory interface circuit, the at least one access request corresponding to the (N+1)-th to M-th sensor data, nor does the prior art teaches to convert the at least one access request into at least one storage access request complying with a storage protocol that supports access to the non-volatile memory device, wherein the integrated controller is configured to store the (N+1)-th to M-th sensor data in the non-volatile memory device based on the at least one storage access request.
Therefore, claim 7 contains allowable subject matter. Claim 8 contains allowable subject matter as it depends from a claim containing allowable subject matter.
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-6 and 9-20 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
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