Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Amendments and arguments filed on 04/02/2026 have been fully considered and are not found to place the application in a condition for allowance.
Specifically, the applicant has provided arguments regarding Sheth not teaching “the claimed buffer positioning and isolation function”. Note, however, that Sheth is simply relied upon for a teaching wherein a buffer provides isolation between two nodes of a gate driving signal. Sheth is not relied upon for teaching an exact positioning of the buffer within the circuit of AAPA. The applicant further asserts that in “Sheth, input/output branches are different with different signals…,without switches, so ‘no shared driving signal, thus no impact’ from output switching on input (no isolation need).” The Office respectfully disagrees. Sheth clearly teaches that “The non-inverting buffer serves to isolate the SRAM current from the effects of loading due to the connection multiple parallel modulation FETs” (see ¶ 102). In other words, similar to the instant application, the buffer of Sheth is used to isolate the input node of a gate driving signal (fig. 5A, Sneg) from the output node (fig. 5A, 514) from the effects of loading due to connection to multiple parallel modulating (or switching) FETs (switches). Accordingly, Sheth clearly teaches a buffer performing a similar function as claimed.
The applicant further asserts that there is no motivation to modify AAPA in view of Sheth. The applicant specifically asserts that “relocation would destabilize input branch feedback without recognized benefit”. While the quoted portion is not found in the specification, the Office respectfully disagrees with such a conclusion. There is no evidence that moving a buffer (voltage follower) would destabilize the branch in any way, accordingly this argument is not found persuasive.
The applicant further asserts that Sheth does not address dynamic switching transients in a shared-signal current mirror. As noted above, Sheth clearly teaches isolating the input node of a gate driving signal (fig. 5A, Sneg) from the output node (fig. 5A, 514) from the effects of loading due to connection to multiple parallel modulating (or switching) FETs (switches). Accordingly, the teachings of Sheth are found to be obviously applicable to the circuit of AAPA.
Furthermore, the applicant asserts that “relocating the buffer risks weakening input branch drive capability”. The Office maintains that Sheth clearly teaches providing a buffer between the input and output nodes of a gate driving signal, making it obvious to one of ordinary skill to relocate the buffer accordingly, expecting to drive the gate driving signal while achieving isolation from the effects of loading due to the switching operations of multiple parallel switches. The combination of AAPA in view of Sheth further teaches the “unexpected results” of improving the “display quality/stability” by stabilizing the gate driving signal using the buffer. Accordingly, the arguments are not found persuasive and the amendments are found to be taught according to AAPA in view of Sheth.
Claim Objections
Claims 1-3 are objected to because of the following informalities: the claims recite “the least one buffer”. Suggested amendment: “the at least one buffer”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over applicant’s admitted prior art, (figures 2-5c of the current application labeled as prior art and its related text in the specification) hereinafter “Aapa”, in view of Sheth et al., US 2022/0165208 A1, hereinafter “Sheth”.
Regarding claim 1, Aapa teaches a power supply circuit (fig. 2, ¶ 36) comprising: a reference circuit (fig. 4, element 10, ¶ 36), configured to generate a reference current (¶ 37); a current mirror circuit (fig. 4, element 30, ¶ 55), configured to be coupled with the reference circuit and mirror the reference current to a plurality of output currents (¶ 57), wherein the current mirror circuit comprises: a gate driver (fig. 4, element 33, ¶ 57), configured to generate a gate driving signal (fig. 4, Vg, ¶ 57) according to a first reference voltage (fig. 4, Vcres, ¶ 62); an input branch (fig. 4, element 31), which receives the gate driving signal and generates an input current according to the gate driving signal (fig. 4, see Vg which controls NM0 which generates input current I1); and a plurality of output branches (fig. 4, elements 32-1 to 32-n), each of which receives the gate driving signal (each output branch receives Vg; ¶ 38 and 57), and generates one of the plurality of output currents according to the gate driving signal (fig. 4, ¶ 57).
Aapa does not teach at least one buffer, configured to be coupled with the gate driver to buffer the gate driving signal; and that each of the output branches receives the gate driving signal through a buffer between the input branch and the plurality of output branches.
Sheth, however, teaches at least one buffer (fig. 5A, buffer 563a and or 563b, ¶ 102), configured to be coupled with the gate driver to buffer the gate driving signal (see ¶ 102), an input branch, which receives the gate driving signal without passing through the at least one buffer (fig. 5A, Sneg node arrives at the buffer without passing through another buffer); and that each of the output branches receives the gate driving signal (fig. 5A, Sneg signal which drives the gate of transistors 534a and 534b, ¶ 102) through the at least one buffer (see ¶ 102) between the input branch and the plurality of output branches (fig. 5A: the buffer is placed between the input and output branches 514 and 561, ¶ 113).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Aapa in view of Sheth. The references teach current mirror driving circuits and Sheth further teaches details regarding inclusion of buffers between the input and output branches of such circuits. One would have been motivated to make such a combination in order to achieve a higher quality display device because Sheth clearly teaches that the “buffer serves to isolate the SRAM current from the effects of loading due to the connection [of] multiple parallel modulation FETs” (¶ 102).
Regarding claim 2, Aapa teaches that the plurality of output branches are coupled through a common driving line (fig. 4, driving line 41, ¶ 60).
Aapa does not specifically teach that the plurality of output branches are coupled with the at least one buffer through a common driving line, so that the at least one buffer is shared by the plurality of output branches.
Sheth teaches that the “buffer serves to isolate the SRAM current from the effects of loading due to the connection [of] multiple parallel modulation FETs”; ¶ 102.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Aapa in view of Sheth. Aapa clearly teaches a common driving line connected to a plurality of output branches and Sheth teaches the connection of buffers to a plurality of output branches. One would have been motivated to incorporate such buffers “to isolate the SRAM current from the effects of loading due to the connection [of] multiple parallel modulation FETs” as taught by Sheth in ¶ 102, thereby achieving a higher quality display device.
Regarding claim 3, Aapa does not specifically teach that each of the plurality of output branches is coupled with one of a plurality of buffers through respective one of a plurality of driving lines, so that the at least one buffer is dedicated to one of the plurality of output branches.
Sheth, however, teaches that the “buffer serves to isolate the SRAM current from the effects of loading due to the connection [of] multiple parallel modulation FETs”; ¶ 102. Sheth, further teaches that buffers may be “added as needed”.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Aapa in view of Sheth to include a buffer for each output branch. Sheth clearly teaches that the buffer serves to isolate the input and output branches from effects of loading, therefore one would have been motivated to include such a buffer at any node of the circuit wherein such an isolation may be beneficial in order to achieve a higher quality display.
Regarding claim 4, Aapa teaches that the input branch comprises: a plurality of first switches (fig. 4, K0); and a plurality of first transistors (fig. 4, NM0), wherein a drain of each of the first transistors receives the reference current at an input terminal of the input branch, respectively; a gate of each of the first transistors receives the gate driving signal through one of the plurality of first switches; and a source of each of the first transistors is grounded (see fig. 4).
Regarding claim 5, Aapa teaches that the gate driver comprises: a first operational amplifier (fig. 4, OP3, ¶ 62), an inverting input terminal of the first operational amplifier receiving the first reference voltage, and a non-inverting input terminal of the first operational amplifier being coupled to the input terminal of the input branch, and an output terminal of the first operational amplifier being coupled to the gate of each of the first transistors through one of the first switches (see fig. 4).
Regarding claim 6, Aapa teaches that each of the plurality of first transistors is an NMOS transistor (fig. 4, NM0 transistors are NMOS).
Regarding claim 7, Aapa teaches that each of the plurality of output branches comprises: a plurality of second switches (fig. 4, K1); a plurality of second transistors (NM11); an output transistor (NM12); and a second operational amplifier (OP2), wherein a non-inverting input terminal of the second operational amplifier is coupled to the input terminal of the input branch, and an output terminal of the second operational amplifier is coupled to the output transistor, a drain of each of the second transistors is coupled to an inverting input terminal of the second operational amplifier, a gate of each of the second transistors is coupled to the output terminal of the first operational amplifier through one of the plurality of second switches, and a source of each of the second transistors is grounded (fig. 4, ¶ 60).
Regarding claim 8, Aapa teaches that each of the plurality of second transistors is an NMOS transistor (fig. 4, NM11 transistors are NMOS).
Regarding claim 9, Aapa teaches that the power supply circuit further comprises: a controller (fig. 4, controller 1), configured to control on and off states of the plurality of first switches and the plurality of second switches, so as to change current ratios of the plurality of output branches (¶ 61).
Regarding claim 10, Aapa teaches that the controller determines the current ratios of the plurality of output branches according to specifications of a display screen (¶ 75).
Regarding claim 11, Aapa teaches that the controller determines the current ratios of the plurality of output branches according to grayscale levels of pixels of an image (¶ 75: “different brightness requirements” represents grayscale levels of pixels of an image).
Regarding claim 12, Aapa teaches that the controller determines predetermined current ratios of the plurality of output branches and duty ratios of the plurality of output currents according to grayscale levels of pixels of an image (¶ 75: “different brightness requirements” represents grayscale levels of pixels of an image which is achieved based on current ratio or duty ratios of the current signals).
Regarding claim 13, Aapa teaches that the reference circuit comprises: an operational amplifier (fig. 4, OP1), wherein an inverting input terminal of the operational amplifier receives a second reference voltage (Vref); and an external resistor (Rext), wherein a first terminal of the external resistor is coupled to a non-inverting input terminal of the operational amplifier, and a second terminal of the external resistor is grounded (see fig. 4, ¶ 40).
Regarding claim 14, Aapa teaches that the reference circuit further comprises: a third transistor (fig. 4, PM0), wherein a gate of the third transistor is coupled to an output terminal of the operational amplifier, a drain of the third transistor is coupled to the first terminal of the external resistor, and a source of the third transistor is grounded (see fig. 4, ¶ 40); and a fourth transistor (fig. 4, PM1), wherein a gate of the fourth transistor is coupled to the output terminal of the operational amplifier, a drain of the fourth transistor is respectively coupled to the drain of each of the first transistors, and a source of the fourth transistor is grounded (see fig. 4, ¶ 46).
Regarding claim 15, Aapa teaches a driver chip, comprising the power supply circuit according to claim 1 (see rejection of claim 1), wherein the power supply circuit provides the plurality of output currents to light-emitting diodes to display an image (¶ 52 and ¶ 74-75).
Regarding claim 16, Aapa teaches a display screen (¶ 75), comprising: a plurality of light-emitting diodes (fig. 5a, LED is one pixel of the display screen); and the driver chip according to claim 15 (see rejection of claim 15), wherein anodes of the plurality of light-emitting diodes are coupled to a control line, and cathodes of the plurality of light-emitting diodes are coupled to respective ones of a plurality of output terminals of the driver chip (see fig. 5a, configuration of the LED); or cathodes of the plurality of light-emitting diodes are coupled to a control line, and anodes of the plurality of light-emitting diodes are coupled to respective ones of a plurality of output terminals of the driver chip.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621
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