Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 02/17/2025. Claims 1-20 are pending on this application.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation “the digital-to-analog converter circuit”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1, 2, 9, and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang Pub. No. 2013/0050003.
Regarding claim 1. Fig. 6 of Wang et al. discloses a capacitive sensing circuit (CS3,CS4), comprising: a switched capacitor charge to voltage converter circuit (switched capacitor of 24) having an input (+/- input of 24) coupled to capacitive Sensor (CS3, CS4) and configured to receive a negative feedback signal (feedback of DAC switching capacitor CS1, CS2) ; an offset and low-frequency noise (paragraph 0039 discloses “the auto-zero feature reduces offset and the 1/f noise”) cancelation circuit (Cs, switch Vcm, and switch P2) having an input of CS) coupled to an output of the switched capacitor C2V converter circuit (23) ; and a sigma-delta analog-to-digital converter circuit (Int 2, 16; paragraph 0033) including a loop filter (Int 2) coupled to an output of the offset and low-frequency noise cancelation circuit (output of P2) , a quantizer (16) coupled to an output of the loop filter (output of Int 2) and configured to generate a digital signal (28) , and a digital-to-analog converter circuit (switching capacitor of CS1 and CS2) configured to generate the negative feedback signal (feedback of DAC switching capacitor CS1, CS2) from the digital signal (28).
Regarding claim 2. The circuit of claim 1, Fig. 6 of Wang further discloses wherein the digital signal (28) is indicative of a sensed capacitive variation (sensor variation of CS3, CS4) of the capacitive sensor (CS3, CS4).
Regarding claim 9. The circuit of claim 1, Fig. 6 of Wang further discloses wherein the switched capacitor C2V converter circuit (switched capacitor of 24) comprises: an amplifier (24) having an input and an output (input and output of 24) ; a capacitor Cia) coupled between the input and output of the amplifier (input and output of 24) ; and a switch (P1e, Pif) , controlled by a reset signal (reset signal of pie and p1f) , to selectively connect the input (input of 24) of the amplifier to a reset voltage (output and input having the same voltage when pie or pif is on).
Regarding claim 11. The circuit of claim 1, wherein the offset and low-frequency noise cancelation circuit (Cs, switch Vcm, and switch P2) comprises a capacitor (CS) having a first terminal (first terminal of CS) coupled to the output of the switched capacitor C2V converter circuit (output of 24) and a switching circuit (switch Vcm, and switch P2) configured to connect a second terminal of the capacitor (second terminal of CS) to a reset voltage (Vcm) in response to assertion of a control signal (control signal of switching Vcm) and connect the second terminal of the capacitor (second terminal of CS) to an input of the sigma-delta ADC circuit (Int 2 and 16) in response to deassertion of the control signal (deassertion of Vcm switch signal).
Regarding claim 12. The circuit of claim 11, wherein the offset and low-frequency noise cancelation circuit (Cs, switch Vcm, and switch P2) is differential (differential of (Cs, switch Vcm, and switch P2) and the reset voltage is a common mode voltage (Vcm).
Regarding claim 13. The circuit of claim 1, wherein the offset and low-frequency noise cancelation circuit (Cs, switch Vcm, and switch P2) is an auto-zeroing (AZ) circuit ((paragraph 0039 discloses “the auto-zero feature reduces offset and the 1/f noise”).
Regarding claim 14. The circuit of claim 1, Fig. 6 further discloses wherein the negative feedback signal output by the digital- to-analog converter circuit (feedback of DAC switching capacitor CS1, CS2) is directly connected to the input of the switched capacitor C2V converter circuit (24).
Regarding claim 15. Fig. 6 of Wang discloses a method, comprising: generating a difference signal (differential input signals of 24) between a capacitive sensor output signal (CS3 and CS4) and a feedback signal (feedback of DAC switching capacitor CS1, CS2); performing offset and low-frequency noise cancelation (Cs, switch Vcm, and switch P2; paragraph 0039 discloses “the auto-zero feature reduces offset and the 1/f noise”) on the difference signal (differing input signals of 24) to generate a first signal (output signal of CS) ; filtering ( Int 2) the first signal (output signal of Cs) to generate a second signal (output signal of Int 2) ; quantizing (16) the second signal (output signal of Int 2) to generate a digital signal (28) ; and performing a digital to analog signal conversion (DAC switching capacitor CS1, CS2) to convert the digital signal (28) to generate the feedback signal (feedback ouput signal of CS1 and CS2).
Regarding claim 16. The method of claim 15, Fig. 6 further discloses wherein generating the difference signal (differential input signals of 24) comprises performing a charge (charge of CS3 and CS4) to voltage (output voltage of 24) conversion operation (output voltage of 24) which converts a charge of the difference signal (charge of differential CS3 and CS4) to a voltage signal (output voltage of 24), and wherein performing offset and low-frequency noise cancelation Cs, switch Vcm, and switch P2; paragraph 0039 discloses “the auto-zero feature reduces offset and the 1/f noise”) is performed on the voltage signal (output voltage of 24) .
Regarding claim 17. The method of claim 16, Fig. 6further comprising directly applying the feedback signal (feedback of DAC switching capacitor CS1, CS2) to an input (+/- input of 24) of the charge to voltage conversion operation (24).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wang applied to claim 1 above in view of Devam et al. Pub. No. 2023/0091543.
Wang applied to claim 1 above does not disclose wherein the switched capacitor C2V converter circuit (switching capacitor of amplified 24) comprises a telescopic cascode amplifier.
Fig. 1 of Devam et al. discloses a delta sigma ADC comprising a telescopic cascode amplifier (112; paragraph 0027).
Wang et al. and Devam et al. are common subject matter of amplifier for delta-sigma ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Devam et al. into Wang et al. for the purpose of provide an amplifier of a specific class when designing an electronic circuit or system usually involves a tradeoff among different performance parameters, e.g., power used by the amplifier, signal noise introduced by the amplifier, area or size of the amplifier.
8 Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang applied to claim 1 above in view of Kinyu Pub. No. 20150171886.
Wang applied to claim 1 applied to claim 9 above, does not disclose wherein the amplifier is a differential amplifier and the reset voltage is a common mode voltage.
Fig. 5 of Kinyu discloses an amplifier circuit (500) comprising: the amplifier (A1) is a differential amplifier (differential of A1) and a reset voltage is a common mode voltage (VCM).
Wang and Kinyu are common subject matter of amplifier; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Kinyu into Wang for the purpose of providing he efficient and accurate conversion (paragraph 0002 of Kinyu).
Allowable Subject Matter
9. Claims 3-7 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein a square wave clock signal is applied to the capacitive sensor, and wherein the digital-to-analog converter circuit includes a tri-level switch circuit that generates the negative feedback signal by capacitively coupling, in response to the digital signal, a selected one of the square wave clock signal, an inversion of the square wave clock signal, and a common mode voltage to an output node where the negative feedback signal is generated.
10. Claims 18-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein the capacitive sensor output signal is generated by a capacitive sensor, further comprising: applying a square wave clock signal is applied to the capacitive sensor; and wherein performing the digital to analog signal conversion comprises generating the feedback signal by capacitively coupling, in response to the digital signal, a selected one of the square wave clock signal, an inversion of the square wave clock signal, and a common mode voltage.
Contact Information
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/28/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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