DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 02/17/2025 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 02/17/2025, 08/28/2026 & 12/05/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 8 & 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6, 8 & 19, the limitations cite “the controller is further configured to determine a filling type of a second group of logic page data by the access circuit and determine the second group of logic page data from the filling type”, it is unclear to examiner what a filling type of a second group is? A word filling is not a technical terminology. Please see [0016] in the current application that possibly describes the filling type includes one of an all 0 sequence or an all 1 sequence. please amend accordingly so that the filling type has to do with logic data either having an all 0 sequence or an all 1 sequence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Nguyen et al (US20220189544).
Regarding claim 1, Nguyen discloses a memory system comprising(FIG 1; 100 comprising 110): a controller comprising at least one of an exclusive OR circuit(FIG 1; [0039] 115 comprising 113 comprising XOR circuit), an inverter, and an access circuit; (FIG 1; [0018, 0027 & 0039] discloses XNOR, access circuit e.g., interface circuitry communicating with 110), and a memory coupled to the controller(140), and the memory comprising at least one memory cell stores m-bit information(FIG 2; 130 comprising memory cell), wherein in is a positive integer greater than 1(FIG 1; [0017-0018] discloses memory cell storing N bits and N-1), wherein, the controller is configured to: in response to received logical page data is configured to n groups of logic page data; generate at least one group of logic page data based on the at least one of the exclusive OR circuit, the inverter, and the access circuit; and transmit m groups of logic page data to the memory, wherein n is a positive integer and less than in m(FIG 1; [0017-0018] discloses generating extra group of data from given data having the reduced number of bits, wherein the extra group of data are generated based on an XOR operation on the reduced numbered of bits N-1) , the m groups of logic page data comprise the n groups of logic page data and the at least one group of logic page data, and the m groups of logic page data comprise m-bit information of the at least one memory cell (FIG 1; [0016-0018 & 0027] discloses controller 115 of 110 to perform operations e.g., reading and writing to the memory cells of 130, wherein programming memory cells at reduced number of bits N-1).
Regarding claim 2, Nguyen discloses wherein the exclusive OR circuit comprises a redundant array of independent disks (RAID) exclusive OR circuit in the controller (FIG 1; [0015] discloses data is encoded with redundant information that is stored in a memory sub-system that comprises 115).
Regarding claim 3, Nguyen discloses wherein the access circuit comprises a direct memory access circuit in the controller (FIG 1; 115 direct connections e.g., interface circuitry communicating with 110).
Regarding claim 4, Nguyen discloses wherein the controller comprises the exclusive OR circuit(FIG 1; [0039] 115 comprising 113 comprising XOR circuit), and the controller is configured to perform an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit to obtain a first group of logic page data(FIG 1 & 4; [0017-0018] discloses generating extra group of data from given data having the reduced number of bits, wherein the extra group of data are generated based on an XOR operation on the reduced numbered of bits N-1).
Regarding claim 5, Nguyen discloses wherein the controller comprises the exclusive OR circuit and the inverter, and the controller is configured to perform an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit to obtain intermediate data(FIG 4; [0061] discloses XOR operation), and perform a NOT operation on the intermediate data by the inverter to obtain a first group of logic page data (FIG 5; [0062] discloses XNOR operation).
Regarding claim 6, Nguyen discloses wherein the controller further comprises the access circuit, and the controller is further configured to determine a filling type of a second group of logic page data by the access circuit and determine the second group of logic page data from the filling type (FIG 6; [0068-0072] discloses different type of group logic pages being access threshold level e.g., XP having all 1s 0-5 Vts and all 0s from 6-13 Vt levels).
Regarding claim 7, Nguyen discloses wherein the controller comprises the access circuit, and the controller is further configured to copy a group of logic page data in the n groups of logic page data by the access circuit to obtain a first group of logic page data (FIG 6; XP and UP on 0-3 Vts having same data values e.g., XP=UP bits on Vts 0-3 levels).
Regarding claim 8, Nguyen discloses wherein the controller is further configured to determine a filling type of a second group of logic page data by the access circuit and determine the second group of logic page data from the filling type (FIG 6; [0068-0072] discloses different type of group logic pages being access threshold level e.g., XP having all 1s 0-5 Vts and all 0s from 6-13 Vt levels).
Regarding claim 9, Nguyen discloses wherein the controller further comprises a first buffer, the first buffer comprises redundant arrays of independent disks (RAID) buffer in the controller, and the controller is further configured to store at least one group of logic page data in the m groups of logic page data by the first buffer (FIG 1; [0015-0018 & 0032] discloses data is encoded with redundant information that is stored in a memory sub-system that comprises 115, wherein 115 includes a buffer memory, discloses memory cell storing N bits and N-1 e.g., by buffer).
Regarding claim 10, Nguyen discloses wherein the memory is configured to generate 2"1 different data states in memory cells based on the m groups of logical page data (FIG 1; [0013 & 0019] discloses memory cell is programmed at one of 2.sup. N levels to represent a combination of values of the predetermined number N of bits, the memory cell can store different combinations of data states).
Regarding claim 11, Nguyen discloses a controller that is configured to couple to a memory comprising at least one memory cell stores m-bit information(FIG 1;140 configured to couple to 130 )having , wherein m is a positive integer greater than 1 (FIG 1; [0017-0018] discloses memory cell storing N bits and N-1), and the controller comprising at least one of an exclusive OR circuit(FIG 1; [0039] 115 comprising 113 comprising XOR circuit), an inverter, and an access circuit; (FIG 1; [0018, 0027 & 0039] discloses XNOR, access circuit e.g., interface circuitry communicating with 110) and the controller is configured to: in response to received logical page data is configured to n groups of logic page data; generate at least one group of logic page data based on the at least one of the exclusive OR circuit, the inverter, and the access circuit; and transmit m groups of logic page data to the memory, wherein n is a positive integer and being less than in m(FIG 1; [0017-0018] discloses generating extra group of data from given data having the reduced number of bits, wherein the extra group of data are generated based on an XOR operation on the reduced numbered of bits N-1), the m groups of logic page data comprise the n groups of logic page data and the at least one group of logic page data, and the in groups of logic page data comprise m-bit information of the at least one memory cell (FIG 1; [0016-0018 & 0027] discloses controller 115 of 110 to perform operations e.g., reading and writing to the memory cells of 130, wherein programming memory cells at reduced number of bits N-1).
Regarding claim 12, Nguyen discloses wherein the exclusive OR circuit comprises a redundant array of independent disks (RAID) exclusive OR circuit in the controller (FIG 1; [0015] discloses data is encoded with redundant information that is stored in a memory sub-system that comprises 115).
Regarding claim 13, Nguyen discloses wherein the access circuit comprises a direct memory access circuit in the controller (FIG 1; 115 direct connections e.g., interface circuitry communicating with 110).
Regarding claim 14, Nguyen discloses wherein the controller comprises the exclusive OR circuit(FIG 1; [0039] 115 comprising 113 comprising XOR circuit), and the controller is configured to perform an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit to obtain a first group of logic page data(FIG 1 & 4; [0017-0018] discloses generating extra group of data from given data having the reduced number of bits, wherein the extra group of data are generated based on an XOR operation on the reduced numbered of bits N-1).
Regarding claim 15, Nguyen discloses an operation method of a memory system(FIG 1 & 5; a method for operating 100 comprising 110), wherein the memory system comprises a controller and a memory coupled with the controller(140 coupled to 130), and the memory comprising at least one memory cell stores m-bit information(FIG 1-3; 130 comprising memory cell storing ) , wherein m is a positive integer greater than 1( FIG 1; [0017-0018] discloses memory cell storing N bits and N-1), and the method comprises: in response to received logical page data, generating n groups of logic page data; generating at least one group of logic page data based on the at least one of an exclusive OR circuit(FIG 1; [0039] 115 comprising 113 comprising XOR circuit), an inverter, and an access circuit(FIG 1; [0018, 0027 & 0039] discloses XNOR, access circuit e.g., interface circuitry communicating with 110); and transmitting m groups of logic page data to the memory, wherein n is a positive integer and being less than m (FIG 1; [0017-0018] discloses generating extra group of data from given data having the reduced number of bits, wherein the extra group of data are generated based on an XOR operation on the reduced numbered of bits N-1), the m groups of logic page data comprise the n groups of logic page data and the at least one group of logic page data, and the in groups of logic page data comprise m-bit information of the at least one memory cell (FIG 1; [0016-0018 & 0027] discloses controller 115 of 110 to perform operations e.g., reading and writing to the memory cells of 130, wherein programming memory cells at reduced number of bits N-1).
Regarding claim 16, Nguyen discloses wherein the exclusive OR circuit comprises a redundant array of independent disks (RAID) exclusive OR circuit in the controller (FIG 1; [0015] discloses data is encoded with redundant information that is stored in a memory sub-system that comprises 115).
Regarding claim 17, Nguyen discloses wherein the access circuit comprises a direct memory access circuit in the controller (FIG 1; 115 direct connections e.g., interface circuitry communicating with 110).
Regarding claim 18, Nguyen discloses wherein generating the at least one group of logic page data based on the at least one of the exclusive OR circuit(FIG 1; [0039] 115 comprising 113 comprising XOR circuit, the inverter, and the access circuit comprises), (FIG 1; [0018, 0027 & 0039] discloses XNOR, access circuit e.g., interface circuitry communicating with 110): selecting the exclusive OR circuit, and performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit to obtain a first group of logic page data(FIG 1 & 4; [0017-0018] discloses generating extra group of data from given data having the reduced number of bits, wherein the extra group of data are generated based on an XOR operation on the reduced numbered of bits N-1).
Regarding claim 19, Nguyen discloses wherein generating the at least one group of logic page data based on the at least one of the exclusive OR circuit, the inverter, and the access circuit comprises: selecting the exclusive OR circuit and the inverter, and performing an exclusive OR operation on the n groups of logic page data by the exclusive OR circuit to obtain intermediate data(FIG 4; [0061] discloses XOR operation), and performing a NOT operation on the intermediate data by the inverter to obtain a first group of logic page data (FIG 5; [0062] discloses XNOR operation); and selecting the access circuit, and determining a filling type of a second group of logic page data by the access circuit and determining the second group of logic page data from the filling type FIG 6; [0068-0072] discloses different type of group logic pages being access threshold level e.g., XP having all 1s 0-5 Vts and all 0s from 6-13 Vt levels).
Regarding claim 20, Nguyen discloses wherein the method further comprises: generating 2" different data states in memory cells based on the m groups of logical page data (FIG 1; [0013 & 0019] discloses memory cell is programmed at one of 2.sup. N levels to represent a combination of values of the predetermined number N of bits, the memory cell can store different combinations of data states).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Piszezek et al (US9639457 FIG 2-3; schematic of RAID engine, and controllers and embedding an XOR logic functions unit to each of controllers).
Rudosky et al (US20120131257 FIG 2 & 16; [0436] discloses controller 325, logic gates AND OR and inverter gates, provides a result based on values of bits stored in storage elements).
Kernahan et al (US20040095116 FIG 6, 11 & 51C discloses interface, controller and exclusive OR gate).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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