Prosecution Insights
Last updated: November 03, 2026
Application No. 19/055,361

Downselector for Sensing Electrode Voltages in an Implantable Stimulator Device

Non-Final OA §102§103
Filed
Feb 17, 2025
Priority
Feb 26, 2024 — provisional 63/557,931
Examiner
SIRCAR, ALISHA JITENDRA
Art Unit
3792
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Boston Scientific Corporation
OA Round
1 (Non-Final)
55%
Grant Probability
Moderate
1-2
OA Rounds
1y 4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 55% of resolved cases
55%
Career Allowance Rate
17 granted / 31 resolved
-15.2% vs TC avg
Strong +52% interview lift
Without
With
+51.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
36 currently pending
Career history
89
Total Applications
across all art units

Statute-Specific Performance

§101
11.7%
-28.3% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 31 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The Information Disclosure Statements (IDS) dated 02/17/2025 and 05/15/2025 have been considered by the Examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5, 8-11, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stanslaski et al (US 20150119751 A1). Regarding claims 1-5, Stanslaski teaches a stimulator device (100), comprising: a plurality of electrode nodes (118/120), wherein each of the electrode nodes is associated with a different electrode configured to contact a patient's tissue (see [0024]; sensing lead 114 includes a lead body 116 and one or more electrodes 118, 120 that are positioned in proximity to the stimulation site within the body of the patient); at least one sense amplifier (312) comprising a first input and configured to sense a signal from the patient's tissue (see [0037]; filtered signals 310 are provided as input to conventional amplifier 312 that scale the amplitude as desired to produce the sensed signal output 314); and a plurality of first switching networks (302/304) each comprising a first switch (604) and a second switch (608) connected in series between one of electrode nodes and the first input (see Fig. 6, [0045]; first switch 604 and second switch 608 connected in series between signal 602 from electrodes 118 or 120 and output signal 610 which is provided to filters 310 to input to amplifier 312), and a third switch (606) connected between a reference voltage and a node between the first and second switches (see Fig. 6; third switch 606 connected between reference voltage and node between first and second switches 604 and 606), wherein each of the first switching networks is controllable by at least one first control signal (see [0045]; the switches are controlled by blanking control signal 306 and inverted blanking control signal 307). Regarding claim 2, Stanslaski teaches the stimulator device of claim 1, wherein each at least one first control signal comprises a first signal and a second signal, wherein the second signal is a logical complement of the first signal (see Fig. 6, [0045]; first control signal comprises blanking control signals 306 and 307, where series switches 604 and 608 are controlled by blanking control signal 306 and parallel switch 606 is controlled by inverted blanking control signal 307). Regarding claim 3, Stanslaski teaches the stimulator device of claim 2, wherein the first signal controls the first and second switches, and wherein the second signal controls the third switch (see Fig. 6, [0045]; first control signal comprises blanking control signals 306 and 307, where series switches 604 and 608 are controlled by blanking control signal 306 and parallel switch 606 is controlled by inverted blanking control signal 307). Regarding claim 4, Stanslaski teaches the stimulator device of claim 2, wherein the first switch comprises a first transfer gate, and wherein the second switch comprises a second transfer gate (see Fig. 7, [0046-0047]; Fig. 7 shows an example blanking switch configuration which may be implemented for any of switches 302, 304, 604, 606, and 608 including transistors M1, M2, and M3). Regarding claim 5, Stanslaski teaches the stimulator device of claim 4, wherein the first and second transfers gates each comprise a N-channel and P-channel transistor connected in parallel (see Fig. 7, [0046-0047]; the blanking switch is formed by the interconnection of three individual transistors 702, 704, 706 rather than a single one; M1 transistor 702 having a substrate 724 receives the sensed signal from the electrode 118 or 120 at a node 714 such as a FET drain, receives the blanking control signal from the controller 202 at a node 716 such as a FET gate, and outputs the sensed signal 726 when conducting from a node 718 such as a FET source; n-well 722 receives a supply voltage 710 while the p-well 712 is to ground, the voltage across the p-well 720 of the M1 transistor 702 is set through the M2 transistor 704 and the M3 transistor 706). Regarding claim 8, Stanslaski teaches the stimulator device of claim 1, wherein the reference voltage comprises ground (see Fig. 6, [0045]; parallel-to-ground blanking control switch 606). Regarding claim 9, Stanslaski teaches the stimulator device of claim 1, wherein each first switching network is configured so that the first and second switches are closed at the same time that the third switch is opened (see [0045]; first control signal comprises blanking control signals 306 and 307, where series switches 604 and 608 are controlled by blanking control signal 306 and parallel switch 606 is controlled by inverted blanking control signal 307, the series switches 604, 608 are controlled by the blanking control signal 306 as to conduct current except during the time including the stimulation pule and the peak recharge pulse), and the first and second switches are opened at the same time that the third switch is closed (see [0045]; the parallel switch 606 is controlled by an inverted blanking control signal 307 such that the switch 606 only conducts current during the time including the stimulation pulse and the peak of the recharge pulse). Regarding claim 10, Stanslaski teaches the stimulator device of claim 1, wherein the at least one first control signals are issued by control circuitry (see [0036]; the controller 202 provides a blanking control signal 306). Regarding claim 11, Stanslaski teaches the stimulator device of claim 10, wherein the control circuitry is powered by a first power supply voltage (see Fig. 2, [0032-0035]; the controller 202 orchestrates the operation of the sensing circuit and the stimulation engine 206, wherein the controller 202 controls the threshold being applied by signal limiters of the sensing circuit 204 to limit the signal amplitude, such as the voltage, of the stimulation signal and recharge signal being captured). Regarding claim 18, Stanslaski teaches the stimulator device of claim 1, wherein the at least one sense amplifier comprises a second input, and further comprising a plurality of second switching networks (302/304) each comprising a first switch (604) and a second switch (608) connected in series between the second input and one of the electrode nodes (see Fig. 6, [0045]; first switch 604 and second switch 608 connected in series between signal 602 from electrodes 118 or 120 and output signal 610 which is provided to filters 310 to input to amplifier 312; note that the circuit depicted in Fig. 6 may represent either/both of switch networks 302 and 304), a third switch (606) connected between a reference voltage and a node between the first and second switches (see Fig. 6; third switch 606 connected between reference voltage and node between first and second switches 604 and 606), wherein each of the second switching networks is controllable by at least one second control signal (see [0036]; controller 202 provides a blanking control signal 308 that causes the switches to either conduct signals or stop conducting the signals from the electrodes 118, 120). Regarding claim 19, Stanslaski teaches the stimulator device of claim 18, further comprising control circuitry configured to issue the at least one first control signal and the at least one second control signal (see [0036]; controller 202 provides a blanking control signal 306, 308 that causes the switches to either conduct signals or stop conducting the signals from the electrodes 118, 120). Regarding claim 20, Stanslaski teaches the stimulator device of claim 19, wherein the control circuitry is configured to issue the at least one first control signal and the at least one second control signal to couple different of the electrode nodes to the first and second inputs (see [0036]; controller 202 provides a blanking control signal 306, 308 that causes the switches to either conduct signals or stop conducting the signals from the electrodes 118, 120; wherein the blanking control signals cause the electrode nodes 118, 120 to couple to the filters 310 to be input to amplifiers 312). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Stanslaski et al (US 20150119751 A1) in view of Andreu et al (US 20080061630 A1). Regarding claim 5, Stanslaski teaches the stimulator device of claim 4 wherein the first and second transfer gates each comprise a N-channel transistor and a P-channel transistor. Andreu teaches a stimulation device for distributing power amongst cathodes of a multipolar electrode system, including a first and second transfer gate (Fig. 15B) each comprising a N-channel and P-channel transistor connected in parallel (see Andreu [0190]; CMOS transmission gates consisting of an N channel transistor and P channel transistor placed in parallel). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s transfer gates with Andreu’s CMOS transmission gates comprising a N-channel and P-channel transistor connected in parallel. One of ordinary skill in the art would have been motivated to make this modification in order to implement a circuit architecture which is less constraining in terms of deviation from Vref (Andreu [0190]). Regarding claim 6, Stanslaski and Andreu teach the stimulator device of claim 5. Stanslaski is silent regarding wherein the first signal controls the N-channel transistors in the first and second transfer gates, and wherein the second signal controls the P-channel transistors in the first and second transfer gates. Andreu teaches wherein the first signal controls the N-channel transistors in the first and second transfer gates (see Andreu [0190]; CMOS transmission gates consisting of an N channel transistor and a P channel transistor placed in parallel and controlled by complementary signals at the gates thereof), and wherein the second signal controls the P-channel transistors in the first and second transfer gates (see Andreu [0190]; CMOS transmission gates consisting of an N channel transistor and a P channel transistor placed in parallel and controlled by complementary signals at the gates thereof). It can be appreciated that the device of Stanslaski has established that the first and second control signals are of complementary types. It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s transfer gates with Andreu’s CMOS transmission gates comprising a N-channel and P-channel transistor connected in parallel. One of ordinary skill in the art would have been motivated to make this modification in order to implement a circuit architecture which is less constraining in terms of deviation from Vref (Andreu [0190]). Regarding claim 7, Stanslaski and Andreu teach the stimulator device of claim 6. Stanslaski further teaches wherein the second signal also controls and the third switch (se Stanslaski [0045]; first control signal comprises blanking control signals 306 and 307, where series switches 604 and 608 are controlled by blanking control signal 306 and parallel switch 606 is controlled by inverted blanking control signal 307). Claims 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Stanslaski et al (US 20150119751 A1) in view of Weerakoon et al (US 20210268269 A1). Regarding claim 12, Stanslaski teaches the stimulator device of claim 11. Stanslaski is silent regarding wherein the at least one first control signals are established in a second domain comprising a second power supply voltage higher than the first power supply voltage. Weerakoon teaches a stimulation device comprising a plurality of electrode nodes wherein each of the electrode nodes is associated with a different electrode configured to contact a patient’s tissue (Weerakoon, Abstract), wherein the control circuitry (170/172) is powered by a first power supply voltage (see Weerakoon Fig. 4B; power source 14 supplying power supply voltage Vbat), wherein the at least one first control signals are established in a second domain comprising a second power supply voltage higher than the first power supply voltage (see Weerakoon [0125-0128]; the control signals sent to the PDACs and NDACs are references to the appropriate power domain, wherein the PDACs operate in the VH/Vssh high power domain). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s stimulator device with a first power supply and second power supply higher than the first power supply as taught by Weerakoon. One of ordinary skill in the art would have been motivated to make this modification in order to keep elements of the circuitry which require different voltages for their control signals, such as the PDACs and NDACs, operating in their appropriate power domain at a power efficient level (Weerakoon [0081], [0116-0118]). Regarding claim 13, Stanslaski and Weerakoon teach the stimulator device of claim 12. Stanslaski is silent regarding the device further comprising level translator circuitry to produce the at least one first control signals from control signals established in a first domain comprising the first power supply voltage. Weerakoon teaches the device further comprising level translator circuitry to produce the at least one first control signals from control signals established in a first domain comprising the first power supply voltage (see Weerakoon [0125-0128]; the control signals sent to the PDACs and NDACs are references to the appropriate power domain, the control signals are issued from the pulse definition circuits, PDCs, which are powered by Vcc and ground and operate in the same power domain as the NDACs so the NDACs can receive their control signals directly from the PCDs while the control signals for the PDACs are sent to a level elevator 230 to increase the voltage of the signal). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s stimulator device with level translator circuitry as taught by Weerakoon. One of ordinary skill in the art would have been motivated to make this modification in order to keep elements of the circuitry which require different voltages for their control signals, such as the PDACs and NDACs, operating in their appropriate power domain at a power efficient level (Weerakoon [0081], [0116-0118]). Regarding claim 14, Stanslaski and Weerakoon teach the stimulator device of claim 12. Stanslaski is silent regarding the device further comprising a boost circuit configured to generate a boosted power supply voltage higher than the first power supply voltage. Weerakoon teaches the device further comprising a boost circuit configured to generate a boosted power supply voltage higher than the first power supply voltage (see Weerakoon Fig. 14C, [0128]; level elevator 230 to increase the voltage of the signal from the first power supply voltage/low power domain). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s stimulator device with a boost circuit configured to generate a boosted power supply as taught by Weerakoon. One of ordinary skill in the art would have been motivated to make this modification in order to keep elements of the circuitry which require different voltages for their control signals, such as the PDACs and NDACs, operating in their appropriate power domain at a power efficient level (Weerakoon [0081], [0116-0118]). Regarding claim 15, Stanslaski and Weerakoon teach the stimulator device of claim 14. Stanslaski is silent regarding wherein the second power supply voltage comprises the boosted power supply voltage. Weerakoon teaches wherein the second power supply voltage comprises the boosted power supply voltage (see Weerakoon Fig. 14C, [0128]; level elevator 230 to increase the voltage of the signal from the first power supply voltage/low power domain into the high power domain). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s stimulator device with a boost circuit configured to generate a boosted power supply as the second power supply as taught by Weerakoon. One of ordinary skill in the art would have been motivated to make this modification in order to keep elements of the circuitry which require different voltages for their control signals, such as the PDACs and NDACs, operating in their appropriate power domain at a power efficient level (Weerakoon [0081], [0116-0118]). Regarding claim 16, Stanslaski and Weerakoon teach the stimulator device of claim 12. Stanslaski is silent regarding the device further comprising stimulation circuitry configured to issue stimulation to the plurality of electrode nodes, wherein the stimulation circuitry is powered by a compliance power supply voltage. Weerakoon teaches the device further comprising stimulation circuitry configured to issue stimulation to the plurality of electrode nodes (see Weerakoon Fig. 4B; stimulation circuitry 170), wherein the stimulation circuitry is powered by a compliance power supply voltage (see Weerakoon [0095]; compliance voltage generation block 76 that produces the compliance voltage VH power supply for the DACs). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s stimulator device with stimulation circuitry power by a compliance power supply voltage as taught by Weerakoon. One of ordinary skill in the art would have been motivated to make this modification in order to deliver a therapeutic stimulation using a compliance power supply which may vary to keep the stimulation elements operating a power-efficient level (Weerakoon [0081]). Regarding claim 17, Stanslaski and Weerakoon teach the stimulator device of claim 16. Stanslaski is silent regarding the device further comprising a selector circuit configured to establish the second power supply voltage at a higher of the boosted and compliance power supply voltages. Weerakoon teaches the device further comprising a selector circuit configured to establish the second power supply voltage at a higher of the boosted and compliance power supply voltages (see Weerakoon [0128]; the PDACs operate in the VH/Vssh high power domain so each of the control signals for the PDAC is sent to a level elevator 230 to increase the voltage of the signal). It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Stanslaski’s stimulator device with a selector circuit configured to establish a desired second power supply as taught by Weerakoon. One of ordinary skill in the art would have been motivated to make this modification in order to keep elements of the circuitry which require different voltages for their control signals, such as the PDACs and NDACs, operating in their appropriate power domain at a power efficient level (Weerakoon [0081], [0116-0118]). Conclusion The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Denison (US 20050218911 A1) which teaches a method for enhancing the linearity of a differential capacitive sensor. Lee (US 20140277269 A1) which teaches a high voltage monitoring successive approximation analog to digital converter. Reinke et al (US 20140277283 A1) which teaches an implantable medical device having a power supply for generating a regulated power supply. Marnfeldt et al (US 20130289665 A1) which teaches real time compliance voltage generation for an implantable stimulator. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALISHA J SIRCAR whose telephone number is (571)272-0450. The examiner can normally be reached Monday - Thursday 9-6:30, Friday 9-5:30 CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Klein can be reached at 571-270-5213. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.J.S./Examiner, Art Unit 3792 /Benjamin J Klein/Supervisory Patent Examiner, Art Unit 3792
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Prosecution Timeline

Feb 17, 2025
Application Filed
Oct 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
55%
Grant Probability
99%
With Interview (+51.6%)
3y 1m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
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