DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokomizo (US Pat. App. Pub. No. 2020/0343048).
With respect to claim 1, Yokomizo discloses a chip electronic component (see abstract) comprising: a multilayer ceramic capacitor (see FIG. 3A and paragraph [0031]); and spacers (see FIG. 3A, elements 20a/20b, and paragraph [0041]); wherein the multilayer ceramic capacitor includes: a multilayer body including a plurality of inner electrode layers and a plurality of inner dielectric layers that are alternately arranged (see FIG. 3A, elements 10A, 14, 16a, and 16b, and paragraph [0035]); and outer electrodes (see FIG. 3A, elements 18a/18b and paragraph [0037]); the multilayer body includes: capacitor principal surfaces opposite to each other in a lamination direction; capacitor side surfaces opposite to each other in a width direction that crosses the lamination direction; and capacitor end surfaces opposite to each other in a length direction that crosses the lamination direction and the width direction (see FIGS. 1-3, elements 12a-12f, and paragraph [0032]); and the outer electrodes are provided on respective ones of the capacitor end surfaces (see FIG. 3); the spacers are provided at both ends of one of the capacitor principal surfaces in the length direction (see FIG. 3), the one of the capacitor principal surfaces being adjacent to a mounting board for the multilayer ceramic capacitor (see FIG. 3, element 12a); and each of the spacers includes spacer principal surfaces opposite to each other in the lamination direction (see FIG. 3, the top and bottom surfaces of the spacers), and at least one recess is provided in a surface of one of the spacer principal surfaces that is adjacent to the mounting board (see FIG. 3B and paragraph [0043], noting that the spacers are filled with pores 24 – up to 40% -- that would include those on the surface area facing the mounting board).
With respect to claim 2, Yokomizo discloses that each spacers includes an intermetallic compound including a high-melting-point metal and a low-melting-point metal as a main component. See paragraph [0042].
With respect to claim 3, Yokomizo discloses that the high-melting-point metal includes at least one of Cu or Ni; and the low-melting-point metal includes Sn. See paragraph [0042].
With respect to claim 5, Yokomizo discloses that a total opening area of each of the at least one recess in each of the spacers is about 25% or more and about 75% or less of a surface area of the one of the spacer principal surfaces that is adjacent to the mounting board. See paragraph [0043], noting a porosity of up to 40% per unit area, including the principal surfaces.
With respect to claim 6, Yokozimo discloses that an opening area of each of the at least one recess in each of the spacers is about 0.1% or more and about 70% or less of a surface area of the one of the spacer principal surfaces that is adjacent to the mounting board. See paragraph [0043], noting a porosity of up to 40% per unit area, including the principal surfaces.
With respect to claim 7, Yokozimo discloses that a depth of each of the at least one recess in the lamination direction is about 1% or more and about 50% or less of a thickness of each of the spacers in the lamination direction. See FIG. 3B and paragraph [0043], noting a porosity of up to 40% per unit area, including the spacer principal surfaces.
With respect to claim 8, Yokozimo discloses that each of the spacers includes two spacer end surfaces that are opposite to each other in the length direction and include recesses in surfaces thereof. See paragraph [0043], noting a porosity of up to 40% per unit area, including the end surfaces.
With respect to claim 9, Yokozimo discloses that each of the spacers includes two spacer side surfaces that are opposite to each other in the width direction and include recesses in surfaces thereof. See paragraph [0043], noting a porosity of up to 40% per unit area, including the side surfaces.
With respect to claim 10, Yokomizo discloses that, in the multilayer body, one of the capacitor end surfaces is defined as a first capacitor end surface, another of the capacitor end surfaces is defined as a second capacitor end surface (see FIG. 3A, surfaces 12e/12f), and one of the capacitor principal surfaces that is adjacent to the spacers is defined as a second capacitor principal surface (see FIG. 3A, surface 12a); each of the spacers includes two spacer end surfaces that are opposite to each other in the length direction (see FIG. 3A, noting that the spacers have a parallelepiped shape), a first of the two spacer end surfaces being defined as a first spacer end surface, and a second of the two spacer end surfaces being defined as a second spacer end surface (see FIG. 3A); the spacers include: a first spacer in contact with a portion of a first outer electrode that is one of the outer electrodes adjacent to the first capacitor end surface, the portion of the first outer electrode extending along the second capacitor principal surface (see FIG. 3A, noting that spacer 20a is in contact with first outer electrode 18a); and a second spacer in contact with a portion of a second outer electrode that is one of the outer electrodes adjacent to the second capacitor end surface, the portion of the second outer electrode extending along the second capacitor principal surface (see FIG. 3A, noting that spacer 20b is in contact with first outer electrode 18b); at least one recess is provided in the first spacer end surface of the first spacer that is adjacent to the first capacitor end surface (see FIG. 3B and paragraph [0043], noting a porosity of up to 40% per unit area, including the first spacer end surface); and at least one recess is provided in the second spacer end surface of the second spacer that is adjacent to the second capacitor end surface (see FIG. 3B and paragraph [0043], noting a porosity of up to 40% per unit area, including the second spacer end surface).
With respect to claim 11, Yokomizo discloses that each of the outer electrodes includes a base electrode layer and a plating layer. See paragraph [0107].
With respect to claim 12, Yokomizo discloses that each of the spacers has a rectangular or substantially rectangular shape. See FIG. 3A and paragraph [0048].
With respect to claim 13, Yokozimo discloses that the spacers have a same shape. See FIG. 3A and paragraph [0048].
With respect to claim 14, Yokomizo discloses that the surface of the one of the spacer principal surfaces that is adjacent to the mounting board is a mounting surface joined to the mounting board. See FIG. 6.
With respect to claim 18, Yokomizo discloses that at least one of the spacer principal surfaces includes projections and recesses. See FIG. 3B and paragraph [0043], noting a porosity of up to 40% per unit area, including the spacer principal surfaces.
With respect to claim 19, Yokomizo discloses that each of the at least one recess has a pointed shape with a decreasing thickness or a shape that is wider inside than at an opening. See FIG. 3B.
With respect to claim 20, Yokomizo discloses that each of the at least one recess has a depth of about 1% to about 50% of a thickness of the respective spacer. See FIG. 3B and paragraph [0043], noting a porosity of up to 40% per unit area, including the spacer principal surfaces.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yokomizo (US Pat. App. Pub. No. 2020/0343048) in view of KR 10-1630037.
With respect to claim 4, Yokomizo fails to teach that each of the spacers includes a conductive resin.
KR ‘037, on the other hand, teaches that spacers include a conductive resin. See FIG. 3B, elements 151/152. Such an arrangement results in a reduction in acoustic noise. See Table 1.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Yokozimo, as taught by KR ‘037, in order to reduce the acoustic noise.
Allowable Subject Matter
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: with respect to claims 15-17, the prior art fails to teach the specificities of the resin/metal spacers, as recited in each claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fujita et al. (US 2019/0287719), Ahn et al. (US 2016/0093441) and Chikuma (US 2022/0199325) each disclose spacers between a ceramic capacitive body and a mounting board, but fail to disclose the recess recited in claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole, can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION R. FERGUSON/Primary Examiner, Art Unit 2847
Prosecution Insights