DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 is indefinite because of the recitation “wherein the output circuit is a flip-flop comprising: a P-type transistor electrically coupled to a power supply terminal and a connection terminal, wherein the connection terminal is electrically coupled to the output terminal; and an N-type transistor electrically coupled between the connection terminal and a ground terminal; wherein the P-type transistor and the N-type transistor are controlled by the delayed signal and generate the output signal at the connection terminal” (emphasis added). It is unclear what is being claimed here. The recited structural limitation such as “a P-type transistor electrically coupled to a power supply terminal and a connection terminal, wherein the connection terminal is electrically coupled to the output terminal; and an N-type transistor electrically coupled between the connection terminal and a ground terminal; wherein the P-type transistor and the N-type transistor are controlled by the delayed signal and generate the output signal at the connection terminal” is not the structural of the flip-flop. Correction and/or clarification is required.
Claim 10 is also rejected due to their dependencies on the base claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the admitted prior art of Saitou et al. (US 2009/0015298; hereinafter referred to as Saitou).
With regard to Claim 1, Saitou discloses in Figs. 5-6 a signal output apparatus having programmable slew rate, comprising a plurality of output units (DELAY11 – DELAY15, DELAY31 – DELAY38, MUX21 -- MUX23, MUX31 and MUX32) electrically coupled in parallel between an input terminal and an output terminal each corresponding to a variable signal delay amount, each of the output units comprising a delay path configured to provide the variable signal delay amount and to receive and delay an input signal (INN, INP) from the input terminal to generate a delayed signal; and an output circuit (B1/B2/B3/B4/B5) to receive the delayed signal and generate an output signal (OUTN, OUTP) to an output terminal; wherein the output terminal inherently outputs a total output signal according to the output signals generated from the output circuits of the output units, and a slew rate of the total output signal is determined by a combination of the variable signal delay amounts of all the output units.
With regard to Claim 2, wherein the output units are categorized into a plurality of output groups, the variable signal delay amount of each of the output units in the output groups is the same and the variable signal delay amounts of the output units in the different output groups are different (as depicted in Fig. 5).
With regard to Claim 3, wherein an equivalent RC time constant of the output units is inherently a product of an equivalent resistance of the output units and a capacitance of a load capacitor at the output terminal, and the number of the output groups and the number of the output units in each of the output groups determine the equivalent RC time constant and further determine a linearity of the slew rate of the total output signal.
With regard to Claim 4, wherein the delay path comprises a multiplexer (MUX21/ MUX22/MUX23/MUX31/MUX32); a first delay sub-path electrically coupled between the input terminal and the multiplexer and having a first delay element number of M to delay the input signal to generate a first delayed signal, wherein M is an integer larger than or equaling to 0; and a second delay sub-path electrically coupled between the input terminal and the multiplexer and having a second delay element number of N that is different from the first delay element number of M to delay the input signal to generate a second delayed signal, wherein N is an integer larger than or equaling to 0; the multiplexer is configured to select one of the first delayed signal and the second delayed signal to be outputted as the delayed signal (as depicted in Fig. 5).
With regard to Claim 5, further comprising a control circuit (not shown, the control circuit that generates signal SELECT in Fig. 5) configured to generate a delay control signal to each of the output units to control the multiplexer to perform selection (as depicted in Fig. 5).
With regard to Claim 6, wherein the delay path of each of the output units comprises: at least one delay element; and at least one bypass element configured to bypass the delay element when being enabled and not bypass the delay element when being disabled (as depicted in Fig. 5).
With regard to Claim 7, further comprising a control circuit configured to generate a delay control signal (SELECT) to each of the output units to enable or disable the bypass element (as depicted in Fig. 5).
With regard to Claim 8, wherein the delay path of at least a part of the output units does not include any delay element (as depicted in Fig. 5).
Conclusion
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/HAI L NGUYEN/Primary Examiner, Art Unit 2836 June 21, 2026
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