DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Amendment
The amendment received on 08/31/2026 has been reviewed and considered with the following results:
As to the rejection to claims 9 and 10, under 35 USC § 112(b) or 35 U.S.C. 112 (pre-AlA), second paragraph. Applicants’ amendment has overcome the prior rejection, as such, the rejection has been withdrawn.
As to the prior art rejections to the claims, under 35 U.S.C. § 102. Applicant’s amendment and remarks with respect to the prior art rejections to the claims, mailed on 6/24/2026, have been considered but are moot in view of the new ground(s) of rejection as set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 7-10 are rejected under 35 U.S.C. § 103 as being unpatentable over Saitou et al. (US 2009/0015298; hereinafter referred to as “Saitou”) in view of Wiktor et al. (US 10,892,769 B2; hereinafter referred to as “Wiktor”).
With regard to Claim 1, Saitou discloses in Figs. 5-6 a signal output apparatus having programmable slew rate, comprising a plurality of output units (DELAY11 – DELAY15, DELAY31 – DELAY38, MUX21 - MUX23, MUX31 and MUX32) electrically coupled in parallel between an input terminal and an output terminal each corresponding to a variable signal delay amount, each of the output units comprising a delay path configured to provide the variable signal delay amount and to receive and delay an input signal (INN, INP) from the input terminal to generate a delayed signal; and an output circuit (B1/B2/B3/B4/B5) to receive the delayed signal and generate an output signal (OUTN, OUTP) to an output terminal; wherein the output terminal outputs a total output signal according to the output signals generated from the output circuits of the output units, and a slew rate of the total output signal is determined by a combination of the variable signal delay amounts of all the output units. In particular, Saitou discloses a plurality of delay elements, including delay elements DELAY 11-DELAY 15 and DELAY 31-DELAY 38, coupled in series. Saitou further discloses that the input signal is delayed by the delay elements and serially transferred through the delay elements to the respective output buffers. Thus, Saitou teaches a delay path comprising at least one delay element for providing a signal delay. Saitou further teaches that the delay amount of the delay elements may be adjusted and that the delay time may be adjusted by changing the number of delay elements. However, Saitou does not expressly disclose the claimed limitation wherein the delay path further comprises “at least one bypass element being a switch, configured to bypass the delay element when being enabled to form a short circuit and not bypass the delay element when being disabled to form an open circuit.” Wiktor discloses a delay element (122, as illustrated in Figs. 1 and 4 of Wiktor) comprising an adjustable delay device 420 and a switch SW1 coupled across the adjustable delay device 420. Wiktor teaches that, when switch SW1 is open, the output signal of delay element 122 is a delayed version of the input signal because the signal propagates through adjustable delay device 420. Wiktor further teaches that, when switch SW1 is closed, the input signal flows through switch SW1, thereby bypassing adjustable delay device 420, such that no additional delay is introduced by the adjustable delay device (see column 2, line 60 through column 3, line 7). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the delay path of Saitou by providing a bypass switch, as taught by Wiktor, coupled across at least one of the delay elements of Saitou, such that when the bypass switch is enabled or closed, a conductive path is provided across the corresponding delay element to bypass the delay element, and when the bypass switch is disabled or open, the bypass path is interrupted such that the input signal propagates through the corresponding delay element. One of ordinary skill in the art would have been motivated to make such a modification in order to selectively include or bypass individual delay elements in the signal path, thereby permitting the amount of delay provided by the delay path to be selectively varied. Such a modification would have involved the use of a known bypass-switch arrangement according to its established function to obtain the predictable result of selectively controlling the number of delay elements contributing to the total signal delay. Accordingly, the claimed limitation requiring “a delay path configured to provide the variable signal delay amount and to receive and delay an input signal from the input terminal to generate a delayed signal, wherein the delay path comprises: at least one delay element; and at least one bypass element being a switch, configured to bypass the delay element when being enabled to form a short circuit and not bypass the delay element when being disabled to form an open circuit” is rendered obvious by Saitou in view of Wiktor.
With regard to Claim 2, wherein the output units are categorized into a plurality of output groups, the variable signal delay amount of each of the output units in the output groups is the same and the variable signal delay amounts of the output units in the different output groups are different (as illustrated in Fig. 5 of Saitou).
With regard to Claim 3, wherein an equivalent RC time constant of the output units is inherently a product of an equivalent resistance of the output units and a capacitance of a load capacitor at the output terminal, and the number of the output groups and the number of the output units in each of the output groups determine the equivalent RC time constant and further determine a linearity of the slew rate of the total output signal.
With regard to Claim 4, wherein the delay path comprises a multiplexer (MUX21/ MUX22/MUX23/MUX31/MUX32); a first delay sub-path electrically coupled between the input terminal and the multiplexer and having a first delay element number of M to delay the input signal to generate a first delayed signal, wherein M is an integer larger than or equaling to 0; and a second delay sub-path electrically coupled between the input terminal and the multiplexer and having a second delay element number of N that is different from the first delay element number of M to delay the input signal to generate a second delayed signal, wherein N is an integer larger than or equaling to 0; the multiplexer is configured to select one of the first delayed signal and the second delayed signal to be outputted as the delayed signal (as illustrated in Fig. 5 of Saitou).
With regard to Claim 5, further comprising a control circuit (not shown, the control circuit that generates signal SELECT, as illustrated in Fig. 5 of Saitou) configured to generate a delay control signal to each of the output units to control the multiplexer (MUX21/ MUX22/MUX23/MUX31/MUX32) to perform selection (as illustrated in Fig. 5 of Saitou).
With regard to Claim 7, further comprising a control circuit (121, as illustrated in Fig. 1 of Wiktor) configured to generate a delay control signal to each of the output units to enable or disable the bypass element (as illustrated in Figs. 1 and 4 of Wiktor).
With regard to Claim 8, wherein the delay path of at least a part of the output units does not include any delay element (as illustrated in Fig. 5 of Saitou).
Claims 9 and 10 are rejected under 35 U.S.C. § 103 as being unpatentable over Saitou in view of Wiktor, as applied to the independent claim 1 above, and further in view of Fertsch et al. (US 11,489,518; hereinafter referred to as “Fertsch”).
With regard to Claim 9, Saitou in view of Wiktor discloses the signal output apparatus of Claim 1 as discussed above. In particular, Saitou discloses in Fig. 5 a signal output apparatus including a delay path comprising a plurality of delay elements and a plurality of output buffers B1-B5 associated with respective stages of the delay path. The input signal is serially transferred through the delay elements, thereby generating respective delayed signals that are provided to the output buffers. Wiktor further discloses in Fig. 4 a delay element comprising an adjustable delay device 420 and a bypass switch SW1 coupled across the adjustable delay device 420. When switch SW1 is open, the signal propagates through adjustable delay device 420 and is delayed, whereas when switch SW1 is closed, the signal propagates through switch SW1 and bypasses adjustable delay device 420. Thus, Saitou in view of Wiktor teaches a delay path having selectively bypassable delay elements for providing a variable signal delay amount.
However, Saitou in view of Wiktor does not expressly disclose that the output circuit is an inverter comprising a P-type transistor electrically coupled to a power supply terminal and a connection terminal, and an N-type transistor electrically coupled between the connection terminal and a ground terminal, wherein the P-type transistor and the N-type transistor are controlled by the delayed signal and generate the output signal at the connection terminal.
Fertsch discloses in Fig. 1 an inverter-based delay element 100 comprising an inverter 110 including a P-type transistor (PMOS FET M2) and an N-type transistor (NMOS FET M3). The gates of PMOS FET M2 and NMOS FET M3 are coupled together to receive an input signal Si, and the drains of PMOS FET M2 and NMOS FET M3 are coupled together to form an output at which output signal So is generated. Thus, PMOS FET M2 and NMOS FET M3 are controlled by the input signal and cooperate to generate the output signal at their common connection terminal.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement at least one of the output buffers of Saitou using the CMOS inverter configuration taught by Fertsch, such that the P-type transistor and N-type transistor are controlled by the corresponding delayed signal and generate the output signal at their common connection terminal. One of ordinary skill in the art would have been motivated to make such a modification because a complementary P-type/N-type transistor inverter was a known circuit configuration for receiving an input signal and generating a corresponding inverted output signal, thereby providing a known implementation of the output-buffer function disclosed by Saitou. Such a modification would have constituted the use of a known circuit configuration according to its established function to obtain the predictable result of generating an output signal in response to the corresponding delayed signal. Accordingly, Claim 9 is rendered obvious over Saitou in view of Wiktor and further in view of Fertsch.
With regard to Claim 10, Saitou in view of Wiktor and Fertsch discloses the signal output apparatus of Claim 9 as discussed above. Fertsch further discloses in Fig. 1 that the inverter-based delay element 100 comprises a first biased load transistor (PMOS FET M1) electrically coupled in series with the P-type transistor (PMOS FET M2) between the power supply terminal VDD and the connection/output terminal formed by the common drains of PMOS FET M2 and NMOS FET M3. Fertsch further discloses a second biased load transistor (NMOS FET M4) electrically coupled in series with the N-type transistor (NMOS FET M3) between the connection/output terminal and the ground terminal VSS. In particular, Fertsch identifies PMOS FET M1 as a current source and NMOS FET M4 as a current sink, with PMOS FET M1, PMOS FET M2, NMOS FET M3, and NMOS FET M4 coupled in series between upper voltage rail VDD and lower voltage rail VSS. The gate of PMOS FET M1 receives a first control or bias voltage VBP, and the gate of NMOS FET M4 receives a second control or bias voltage VBN. Thus, PMOS FET M1 and NMOS FET M4 correspond respectively to the claimed first and second biased load transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further implement the CMOS inverter used as the output circuit of the modified Saitou apparatus with the biased PMOS and NMOS load transistors taught by Fertsch. One of ordinary skill in the art would have been motivated to provide such biased load transistors to control the pull-up and pull-down currents of the inverter and thereby control the timing characteristics of the signal generated by the inverter. Such a modification would have amounted to the application of a known current-starved inverter configuration according to its established function to obtain the predictable result of controlling the electrical and timing characteristics of the inverter output.
Accordingly, Claim 10 is rendered obvious over Saitou in view of Wiktor and further in view of Fertsch.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/HAI L NGUYEN/Primary Examiner, Art Unit 2836 September 15, 2026
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