Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is a response to an application filed on 02/18/2025 in which claims 1-12 are pending and ready for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR20200063969 A (hereinafter KR969).
As to claims 1 and 9, KR969 discloses a maximum power point tracking (MPPT) system (see Fig 3) comprising:
an energy harvesting element (Fig 3, 100);
a switching circuit (Fig 3, Q1, Q2) configured to sample an open circuit voltage of the energy harvesting element as a sampling voltage in an open state (see abstract, lines 1-3), to receive an input voltage from the energy harvesting element through an input node (page 3, parag [0004], the control circuit 200 receives the voltage input from the TEG 100), and to adjust the input voltage based on the sampling voltage in a short-circuit state (see page 3, parag [0005], lines 3-4);
a converter circuit (Fig 3, 300, 400) configured to receive the adjusted input voltage from the switching circuit, and to convert the adjusted input voltage into an output voltage to output the output voltage to an output node (see Fig 3, the converter 300 received the input voltage from TEG 100 and converted the input voltage into the output voltage and supplied it the output node Vout); and
an MPPT control circuit (Fig 3, 200) configured to output a first MPPT control signal and a second MPPT control signal for controlling the maximum power point tracking system to the converter circuit (see abstract),
wherein the first MPPT control signal and the second MPPT control signal are based on a clock signal and have logic values inverted from each other (see page 3, last parag, control sigal Q1 is L, control signal Q2 is H); and
wherein the converter circuit is configured to open or short-circuit the switching circuit based on the first MPPT control signal and the second MPPT control signal (see page 3, parag [0005], lines 5-14; parag [0008], lines 7-10).
As to claim 2, KR969 discloses the MPPT system of claim 1, wherein the energy harvesting element is implemented as one of a thermoelectric energy harvesting element (KR969, see Fig 3, 110), a piezoelectric energy harvesting element, an RF energy harvesting element, and a photoelectric energy harvesting element.
As to claim 3, KR969 discloses the MPPT system of claim 1, wherein the MPPT control circuit is configured to further output the first MPPT control signal and the second MPPT control signal to the switching circuit (see page 3, parag [0006], lines 1-2).
As to claims 4 and 10, KR969 discloses the MPPT system of claim 3, wherein the switching circuit is configured to adjust the input voltage such that a magnitude of the input voltage is half a magnitude of the open circuit voltage of the energy harvesting element, and to transmit the adjusted input voltage to the converter circuit (see page 3, parag [0005], lines 3-4).
As to claim 5, KR969 discloses the MPPT system of claim 4, wherein the switching circuit includes:
a first switch (Fig 3, Q1) connected between the input node and a first sampling node; a second switch (Fig 3, Q2) connected between the first sampling node and a second sampling node; a third switch (Fig 3, switch between Sn2 and Sn3) connected between the second sampling node and a ground node; a first sampling capacitor (Fig 3, Cs1) connected between the first sampling node and the ground node; a second sampling capacitor (Fig 3, Cs2) connected in parallel with the third switch between the second sampling node and the ground node; and an input capacitor (Fig 3, Cin) connected between the input node (Fig 3, Vin node) and the ground node (Fig 3, ground node), and wherein the first switch and the third switch are configured to operate in response to the first MPPT control signal (page 3, lines 5-7, 12-13), and the second switch is configured to operate in response to the second MPPT control signal (see page 3, parag [0005], line 12).
As to claim 6, KR969 discloses the MPPT system of claim 1, wherein the converter circuit is implemented as one of a boost converter (Fig 3, 300), a buck converter (Fig 3, 400), and a buck-boost converter.
As to claims 7 and 11, KR969 discloses the MPPT system of claim 1, wherein the converter circuit includes:
an inductor (Fig 3, L1) connected between the input node and the converting node; a PMOS transistor (Fig 3, Mp) connected between the converting node and the output node; an NMOS transistor (Fig 3, Mn) connected between the converting node and a ground node; and an output capacitor (Fig 3, Cout) connected between the output node (Fig 3, Vout) and the ground node (Fig 3, ground node), and wherein the PMOS transistor (Fig 3, MP) is configured to operate in response to the first MPPT control signal, and the NMOS transistor (Fig 3, MN) is configured to operate in response to the second MPPT control signal (page 3, parag [0005], lines 17-18).
As to claims 8 and 12, KR969 discloses the MPPT system of claim 7, wherein, when the first MPPT control signal is logical high and the second MPPT control signal is logical low, both the NMOS transistor (Fig 3, MN) and the PMOS transistor (Fig 3, MP) are turned off, and the switching circuit is in the open state (see page 3, parag [0007], lines 1-3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2023/0155397 A1; US 2024/0396344 A1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUC M PHAM whose telephone number is (571)272-5026. The examiner can normally be reached 10:00 am - 6:00 pm, Monday to Friday.
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/DUC M PHAM/Examiner, Art Unit 2836 February 15, 2026
/Menatoallah Youssef/SPE, Art Unit 2849