DETAILED ACTION
*Note in the following document:
1. Texts in italic bold format are limitations quoted either directly or conceptually from claims/descriptions disclosed in the instant application.
2. Texts in regular italic format are quoted directly from cited reference or Applicant’s arguments.
3. Texts with underline are added by the Examiner for emphasis.
4. Texts with
5. Acronym “PHOSITA” stands for “Person Having Ordinary Skill In The Art”.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-6 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nvidia (NVIDIA Turing GPU Architecture, downloaded @ https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf, 2018 ).
Regarding Claim 2, Nvidia discloses an apparatus comprising:
a set of memory controllers (p.7 line 3 from the bottom:
PNG
media_image1.png
18
517
media_image1.png
Greyscale
);
a plurality of multi-core groups coupled to the set of memory controllers (p.7
PNG
media_image2.png
192
683
media_image2.png
Greyscale
), wherein a multi-core group within the plurality of multi-core groups (p.7
PNG
media_image3.png
152
459
media_image3.png
Greyscale
)
comprises:
a plurality of graphics cores configured to process one or more shader programs (p.1:
PNG
media_image4.png
88
638
media_image4.png
Greyscale
);
a plurality of tensor cores configured to perform matrix operations (p.4
PNG
media_image5.png
47
642
media_image5.png
Greyscale
);
a ray tracing core configured to perform bounding volume hierarchy (BVH) operations and triangle intersection operations (p.30
PNG
media_image6.png
65
653
media_image6.png
Greyscale
);
a first cache shared among the plurality of graphics cores, the plurality of tensor cores, and the ray tracing core; and a set of register files to store operand values (p.7
PNG
media_image7.png
192
683
media_image7.png
Greyscale
);
wherein execution circuitry of at least one of the plurality of graphics cores, the plurality of tensor cores, and the ray tracing core is configured to:
render a frame of first pixels for a scene (p.72: the noisy images are frames of first pixels for scenes.
PNG
media_image8.png
159
668
media_image8.png
Greyscale
);
perform BVH operations and triangle intersection operations to compute a lighting effect for the scene (see p. Fig.20 Box intersection evaluators and triangle intersection evaluators in RT Core:
PNG
media_image9.png
391
658
media_image9.png
Greyscale
Also see p.30
PNG
media_image10.png
146
664
media_image10.png
Greyscale
and p.79
PNG
media_image11.png
67
665
media_image11.png
Greyscale
); and
perform operations associated with a neural network to generate second pixels having the lighting effect for the scene (p.65
PNG
media_image12.png
73
646
media_image12.png
Greyscale
).
Regarding Claim 3, Nvidia discloses wherein the execution circuitry is configured to denoise the first pixels via the neural network to generate the second pixels (p.72
PNG
media_image13.png
44
667
media_image13.png
Greyscale
).
Regarding Claim 4, Nvidia further discloses wherein the execution circuitry is configured to perform the BVH operations and triangle intersection operations based on a first sample count (p.30
PNG
media_image14.png
58
646
media_image14.png
Greyscale
).
Regarding Claim 5, Nvidia discloses wherein the execution circuitry is configured to generate the second pixels via prediction of pixel data that approximates a second sample count that is higher than the first sample count (p.6
PNG
media_image15.png
62
650
media_image15.png
Greyscale
).
Regarding Claim 6, Nvidia discloses wherein the neural network was trained via training data that corresponds with the second sample count (p.35
PNG
media_image16.png
269
672
media_image16.png
Greyscale
).
Regarding Claims 11-15, Claims 11-15 are similar to Claims 2-6 except in the format of system and the system comprises a memory device. Nvidia discloses
PNG
media_image17.png
87
633
media_image17.png
Greyscale
(p.1). Therefore, the same reasons for rejection applied to Claim 2-6 are also applied to Claim 11-15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-9 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nvidia (NVIDIA Turing GPU Architecture, 2018) as applied to Claims 2 and 11 above, and further in view of Llamas et al. (Coffee Break Series: Ray Tracing in Games with NVIDIA RTX, NVIDIA Developer, Available Online @https://developer.nvidia.com/blog/raytracing-games-nvidia-rtx/, June 20, 2018, 5 pages).
Regarding Claim 7, Nvidia teaches or suggests wherein the first pixels for the scene include a color channel and a normal channel (p.68
PNG
media_image18.png
62
660
media_image18.png
Greyscale
p.50
PNG
media_image19.png
58
636
media_image19.png
Greyscale
).
In addition, Llamas in part 2 video (at 7:28-7:38) discloses that for the denoising the sample value, i.e. the color value, and the normal is used. As Llamas explains ray tracing in games with NVIDIA RTX which implements NVIDIA’s Turing GPU architecture that is described in Nvidia, it would have been obvious to a PHOSITA before the effective filing date of the claimed invention to incorporate the teaching of Llamas and include the limitation of wherein the first pixels for the scene include a color channel and a normal channel in order to create stunning imagery that lives up to the word “photorealistic”. as suggested by Llamas (first paragraph).
Regarding Claim 8, Nvidia teaches or suggests wherein the execution circuitry is configured to generate the second pixels for the scene based at least in part on the color channel and the normal channel (p.68
PNG
media_image18.png
62
660
media_image18.png
Greyscale
p.50
PNG
media_image19.png
58
636
media_image19.png
Greyscale
).
In addition, Llamas in part 2 video (at 7:28-7:38) discloses that for the denoising the sample value, i.e. the color value, and the normal is used. As Llamas explains ray tracing in games with NVIDIA RTX which implements NVIDIA’s Turing GPU architecture that is described in Nvidia, it would have been obvious to a PHOSITA before the effective filing date of the claimed invention to incorporate the teaching of Llamas and include the limitation of wherein the execution circuitry is configured to generate the second pixels for the scene based at least in part on the color channel and the normal channel in order to create stunning imagery that lives up to the word “photorealistic”. as suggested by Llamas (first paragraph).
Regarding Claim 9, Nvidia discloses wherein the execution circuitry is configured to generate the second pixels for the scene via matrix multiplication operations performed via one or more of the plurality of tensor cores (p.4
PNG
media_image20.png
82
645
media_image20.png
Greyscale
p.15
PNG
media_image21.png
45
652
media_image21.png
Greyscale
).
Regarding Claims 16-18, Claims 16-18 are similar to Claims 7-9 except in the format of system. Therefore, the same reasons for rejection applied to Claim 7-9 are also applied to Claim 16-18.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nvidia (NVIDIA Turing GPU Architecture, 2018) as applied to Claims 9 and 18 above, and further in view of Llamas et al. (Coffee Break Series: Ray Tracing in Games with NVIDIA RTX, NVIDIA Developer, Available Online @https://developer.nvidia.com/blog/raytracing-games-nvidia-rtx/, June 20, 2018, 5 pages) as applied to Claim 9 above, and further in view of Kazakov et al. (US 2018/0025463 A1).
Regarding Claim 10, Nvidia modified by Llamas fails to explicitly recite performing the matrix multiplication operations in response to a shader program.
However, Kazakov discloses a PHOSITA before the effective filing date of the claimed invention had already known performing matrix multiplication operations I response to a shader program ([0069]: compiler 22 may compile instructions in vertex shader source code 36 for performing this matrix multiplication).
Therefore it would have been obvious to a PHOSITA before the effective filing date to incorporate the teaching of Kazakov into that of Nvidia and to include the limitation of wherein the execution circuitry is configured to perform the matrix multiplication operations in response to a shader program executed via the plurality of graphics cores in order to utilize a graphics processing unit (GPU) to accelerate the rendering of graphics data for display as suggested by Kazakov ([0002]).
Regarding Claim 19, Claim 19 is similar to Claims 10 except in the format of system. Therefore, the same reason for rejection applied to Claim 10 is also applied to Claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YINGCHUN HE whose telephone number is (571)270-7218. The examiner can normally be reached M-F 8:00-5:00 MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao M Wu can be reached at 571-272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YINGCHUN HE/Primary Examiner, Art Unit 2613
Prosecution Insights