DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/938,984, filed on 9/7/22.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/18/25 and 3/6/25 were considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura et al. (US 2018/0088706, hereinafter “Tanemura”, cited by Applicant) in view of Cheng et al. (TW I412983 B, Machine translation enclosed, hereinafter “Cheng”, cited by Applicant), Lee et al. (US 9,569,035, hereinafter “Lee”, cited by Applicant) and KR 20230020718A (Machine translation enclosed, hereinafter KR ‘718, cited by Applicant). Regarding claim 1, Tanemura discloses a sensing circuit, comprising (Figs. 1, 2, 3A-B, and 4A, system 100): a plurality of first transceiver channels, configured to send and receive a plurality of first detection signals, and the plurality of first detection signals are independent of each other ([0027, 0037, 0039-0040, 0063-0066], Fig. 4A, first mode of operation is absolute or self capacitance sensing techniques with first transceiver capacitors Tx as channels being independent of each other); and a plurality of second transceiver channels, configured to send and receive a plurality of second detection signals, and the plurality of second detection signals are independent of each other, wherein the plurality of first transceiver channels and the plurality of second transceiver channels are alternately arranged to form an array ([0028, 0037, 0041-0044, 0063-0066], Fig. 4A, second transceiver capacitors Rx as second channels are independent of each other and arranged in a checkerboard pattern with the Tx transmitters as first channels which sends and receives a plurality of second detection signals), wherein during a self-capacitance mode, each of the plurality of first transceiver channels and the plurality of second transceiver channels are configured to output and receive a corresponding one of a plurality of self-capacitance signals ([0027, 0037, 0039-0040, 0063-0066], Fig. 4A, first mode of operation is absolute or self capacitance sensing techniques with each of the first transceiver capacitors Tx as first transceiver channels and second transceiver electrodes Rx as second transceiver channels scanning all pixels 205 to output and receive self capacitance signals), wherein during a mutual-capacitance mode, the plurality of first transceiver channels are configured to output a plurality of mutual-capacitance sensing signals, and the plurality of second transceiver channels are configured to receive the plurality of mutual-capacitance sensing signals ([0028, 0037, 0041-0044, 0063-0066], Fig. 4A, second transceiver capacitors Rx as second channels are independent of each other and arranged in a checkerboard pattern with the Tx transmitters as first channels to receive driving signals therefrom during the mutual capacitance sensing mode based on driving signals provided to Tx transmitters), wherein the first transceiver channels and the second transceiver channels output and receive the corresponding one of the plurality of self-capacitance sensing signals during the self-capacitance mode and the first transceiver channels and the second transceiver channels respectively output and receive the mutual-capacitance sensing signals in the mutual-capacitance mode ([0027, 0037, 0039-0040, 0063-0066], Fig. 4A, first mode of operation is absolute or self capacitance sensing techniques with each of the first transceiver capacitors Tx as first transceiver channels and second transceiver electrodes Rx as second transceiver channels scanning all pixels 205 to output and receive self capacitance signals; [0028, 0037, 0041-0044, 0063-0066], Fig. 4A, second mode of operation has second transceiver capacitors Rx as second channels that are independent of each other and arranged in a checkerboard pattern with the Tx transmitters as first transceiver channels, the second transceiver capacitor s Rx receive driving signals during the mutual capacitance sensing mode based on driving signals provided to Tx transmitters), Tanemura does not explicitly disclose a touch signal is determined as a signal triggered by a finger if both the plurality of self-capacitance sensing signals and the plurality of mutual-capacitance sensing signals are received by the array. Cheng discloses using self capacitance detection and mutual capacitance detection to confirm that a user is using a finger for a capacitive touch panel (Machine translation, page 1, last paragraph). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing circuit of Tanemura to have wherein during the self-capacitance mode and the mutual-capacitance mode, a touch signal is determined as a signal triggered by a finger if both the plurality of self-capacitance sensing signals and the plurality of mutual-capacitance sensing signals are received by the array, such as taught by Cheng, for the purpose of confirming a finger touch (Cheng, Machine translation, page 1, last paragraph). Tanemura as modified by Cheng does not explicitly disclose the touch signal is determined as a noise signal if only the plurality of self-capacitance sensing signals are received from the array. Lee teaches using only self capacitance sense signals received from an array to detect noise (Col. 14, lines 9-19). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing circuit of Tanemura as modified by Cheng to have the touch signal is determined as a noise signal if only the plurality of self-capacitance sensing signals are received from the array, such as taught by Lee, for the purpose of detecting noise from a touch signal which can be eliminated as a baseline from a touch signal. Tanemura as modified by Cheng and Lee does not explicitly disclose wherein the touch signal is calibrated or drop frame when the touch signal is determined as the noise signal or the deformation-triggered signal. KR ‘718 teaches wherein if the touch signal is determined as the noise signal, the touch signal is calibrated (Machine translation, page 15, 6th paragraph, at step 830, a calibrated touch input signal is determined based on removing a noise signal from the touch input signal). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing circuit of Tanemura as modified by Cheng and Lee to have wherein if the touch signal is determined as the noise signal, then the touch signal is calibrated, such as taught by KR ‘718, for the purpose of more accurately verifying information on a touch input by reducing noise (KR ‘718, Machine translation page 3, lines 15-16).
Regarding claim 2, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 1, wherein each of the plurality of first transceiver channels comprises a first channel, wherein each of the plurality of second transceiver channels comprises a second channel (Tanemura, [0027-0028, 0037, 0039-0044, 0063-0066], Tx and Rx capacitors are separate first and second capacitors or channels for detecting self and mutual capacitance).
Regarding claim 3, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of the claim 2, wherein the first channel is coupled to the second channel in a first row of the array (Tanemura, Fig. 4A, [0065-0066], single layer of Tx and Rx electrodes has first Tx capacitor or channel coupling to second Rx capacitor or channel in a first row).
Regarding claim 4, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 3, wherein during the self-capacitance mode, the first channel is configured to output a first self-capacitance sensing signal and receive the first self-capacitance sensing signal, and the second channel is configured to output a second self-capacitance sensing signal and receive the second self-capacitance sensing signal (Tanemura, [0027, 0063-0066], self capacitance mode, [0028] sensor electrodes may be transmitters and receivers to have the first capacitance sensing signal from Tx as the sent and received first-self capacitance signal in the first channel and the second self-capacitance sensing signal sent and received from the second capacitor Rx in a second channel in the self capacitance scan mode).
Regarding claim 5, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 4, wherein during the mutual-capacitance mode, the first channel is configured to output a first mutual-capacitance sensing signal, and the second channel is configured to receive the first mutual-capacitance sensing signal (Tanemura, [0028, 0063-0066], mutual capacitance mode, sensing between transmitter electrode Tx as a first channel and receiving electrode Rx as a second channel of driving signal from Tx is first mutual-capacitance sensing signal).
Regarding claim 6, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 4, wherein each of the plurality of first transceiver channels further comprises a third channel, wherein each of the plurality of second transceiver channels further comprises a fourth channel (Tanemura, [0027-0028, 0063-0066], Fig. 4A, in a row there are Tx1 Rx2 Tx3 Rx4 capacitors or channels with Tx3 and Rx4 channels corresponding to third and fourth capacitors or channels).
Regarding claim 7, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 6, wherein the third channel is coupled to the second channel in the first row of the array, wherein the fourth channel is coupled to the third channel in the first row of the array (Tanemura, [0027-0028, 0063-0066], Fig. 4A, in a row there are Tx1 Rx2 Tx3 Rx4 capacitors or channels with Tx1 and Rx2 channels coupled for mutual capacitance sensing, and Tx3 and Rx4 channels coupled for mutual capacitance sensing).
Regarding claim 8, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 7, wherein during the self-capacitance mode, the third channel is configured to output a third self-capacitance sensing signal and receive the third self-capacitance sensing signal, and the fourth channel is configured to output a fourth self-capacitance sensing signal and receive the fourth self-capacitance sensing signal (Tanemura, [0027-0028], in self capacitance mode, capacitors Tx1 Rx2 Tx3 Rx4 as channels each transmit and receive respective first to fourth signals for each capacitor or channel).
Regarding claim 9, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 8, wherein during the mutual-capacitance mode, the third channel is configured to output a second mutual-capacitance sensing signal, and the fourth channel is configured to receive the second mutual-capacitance sensing signal (Tanemura, [0027-0028, 0063-0066], Fig. 4A, in a row there are Tx11 (first row, first column) R12 Tx13 Rx14 capacitors or channels with Tx11 and Rx12 channels coupled for mutual capacitance sensing based on a first driving signal to Tx11 as the first mutual-capacitance sensing signal, and Tx13 and Rx14 channels coupled for mutual capacitance sensing based on a second driving signal to Tx13 channel as the second mutual-capacitance sensing signal).
Regarding claim 10, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 9, wherein during a first self-capacitance operation period of the self-capacitance mode, the first channel is configured to output the first self-capacitance sensing signal and simultaneously receive the first self-capacitance sensing signal, the second channel is configured to output the second self-capacitance sensing signal and simultaneously receive the second self-capacitance sensing signal, the third channel is configured to output the third self-capacitance sensing signal and simultaneously receive the third self-capacitance sensing signal, and the fourth channel is configured to output the fourth self-capacitance sensing signal and simultaneously receive the fourth self-capacitance sensing signal (Tanemura, [0027-0028, 0043, 0045], in self capacitance mode, capacitors Tx11 Rx12 Tx13 Rx14 channels each simultaneously transmit and receive respective first to fourth signals for each capacitor or channel; [0096], simultaneous absolute and mutual capacitive sensing).
Regarding claim 11, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 10, wherein during a first mutual-capacitance operation period of the mutual-capacitance mode, the first channel is configured to output a first mutual-capacitance sensing signal, the second channel is configured to simultaneously receive the first mutual-capacitance sensing signal, the third channel is configured to simultaneously output the second mutual-capacitance sensing signal, and the fourth channel is configured to simultaneously receive the second mutual-capacitance sensing signal (Tanemura, [0027-0028, 0063-0066], Fig. 4A, in a row there are Tx11 (first row, first column) Rx12 Tx13 Rx14 capacitors or channels with Tx11 and Rxs2 channels coupled for mutual capacitance sensing based on a first driving signal to Txs1 channel as the first mutual-capacitance sensing signal, and Tx13 and Rx14 channels coupled for mutual capacitance sensing based on a second driving signal to Tx13 channel as the second mutual-capacitance sensing signal; [0043, 0045, and 0096] teach simultaneous mutual capacitance driving signals and receiving sensing signals).
Regarding claim 12, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 2, wherein the first channel is coupled to the second channel in a first row of the array, wherein each of the plurality of first transceiver channels further comprises a third channel, wherein each of the plurality of second transceiver channel further comprises a fourth channel (Tanemura, [0027-0028, 0063-0066], Fig. 4A, in a first row there are Tx11 (first row, first column) and Rx12 capacitors or channels in the first row, and in a second row there are Rx21 Tx22 capacitors or channels in the second row with Tx22 and Rx21 channels being the third and fourth capacitors or channels).
Regarding claim 13, Tanemura as modified by KR ‘718 discloses the sensing circuit of claim 12, wherein the fourth channel is coupled to the first channel in a first column of the array (Tanemura, [0027-0028, 0063-0066], Fig. 4A; [0067] each Rx electrode or channel is bordered by a plurality of Tx electrodes or channels resulting in the fourth capacitor Rx21 or channel coupled to the first capacitor Tx11 or channel as bordered capacitors providing a channel or channels).
Regarding claim 14, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 13, wherein the third channel is coupled to the fourth channel in a second row of the array, and the third channel is coupled to the second channel (Tanemura, [0027-0028, 0063-0066], Fig. 4A; [0067] wherein the third capacitor Tx22 or channel is coupled to the fourth capacitor Rx21 or channel in a second row of the array, and the third capacitor Tx22 or channel is coupled to the second capacitor Rx12 or channel as a bordering capacitor providing a channel).
Regarding claim 15, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 14, wherein during the self-capacitance mode, the third channel is configured to output a third self-capacitance sensing signal and receive the third self-capacitance sensing signal, and the fourth channel is configured to output a fourth self-capacitance sensing signal and receive the fourth self-capacitance sensing signal (Tanemura, [0027-0028, 0063-0066], Fig. 4A; [0067], during the self-capacitance mode, the third capacitor Tx22 or channel is configured to output a third self-capacitance sensing signal as a driving signal and receive the third self-capacitance sensing signal, and the fourth capacitor Rx21 or channel is configured to output a fourth self-capacitance sensing signal as a driving signal and receive the fourth self-capacitance sensing signal).
Regarding claim 16, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 15, wherein during the mutual-capacitance mode, the third channel is configured to output a second mutual-capacitance sensing signal, and the fourth channel is configured to receive the second mutual-capacitance sensing signal (Tanemura, [0027-0028, 0063-0066], Fig. 4A; [0067], during the mutual-capacitance mode, the third capacitor Tx22 or channel is configured to output a second mutual-capacitance sensing signal as a driving signal, and the fourth capacitor Rx21 or channel is configured to receive the second mutual-capacitance sensing signal).
Regarding claim 17, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 16, wherein during a first self-capacitance operation period of the self-capacitance mode, the first channel is configured to output a first self-capacitance sensing signal and simultaneously receive the first self-capacitance sensing signal, the second channel is configured to output a second self-capacitance sensing signal and simultaneously receive the second self-capacitance sensing signal, the third channel is configured to output the third self-capacitance sensing signal and simultaneously receive the third self-capacitance sensing signal, and the fourth channel is configured to output the fourth self-capacitance sensing signal and simultaneously receive the fourth self-capacitance sensing signal (Tanemura, [0027-0028, 0043, 0045], in absolute or self capacitance mode, capacitors Tx1s Rx12 or channels in the first row and Rx21 Tx22 capacitors or channels in the second row each simultaneously transmit and receive respective first to fourth signals for each capacitor or channel; [0096], simultaneous absolute and mutual capacitive sensing).
Regarding claim 18, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 17, wherein during a first mutual-capacitance operation period of the mutual-capacitance mode, the first channel is configured to output a first mutual-capacitance sensing signal, the second channel is configured to simultaneously receive the first mutual-capacitance sensing signal, the third channel is configured to simultaneously output the second mutual-capacitance sensing signal, and the fourth channel is configured to simultaneously receive the second mutual-capacitance sensing signal (Tanemura, [0027-0028, 0063-0066], Fig. 4A, in a first row there are Tx11 (first row, first column) Rx12 capacitors or channels with Tx11 and Rx2 capacitors or channels are coupled for mutual capacitance sensing based on a first driving signal to Tx11 capacitor or channel as the first mutual-capacitance sensing signal, and in a second row there are Tx22 and Rx21 capacitors or channels coupled for mutual capacitance sensing based on a second driving signal to Tx22 capacitor or channel as the second mutual-capacitance sensing signal; [0043, 0045, and 0096] teach simultaneous mutual capacitance driving signals and receiving sensing signals).
Regarding claim 19, Tanemura as modified by Cheng, Lee and KR ‘718 discloses the sensing circuit of claim 1, wherein a deformation-triggered signal is resulted from a judgment of a change in an air gap between panels, and the presence of the deformation-triggered signal indicates the noise signal (This claim is rejected based on claim 1 which has optional “or” for the deformation-triggered signal, (i.e., wherein the touch signal is calibrated or drop frame when the touch signal is determined as the noise signal or the deformation-triggered signal); since the bolded portion of claim 1 is met, the further limitation of the deformation-triggered signal does not overcome the rejection of claim 1 since this limitation is optional).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tanemura in view of Cheng and Lee. Regarding claim 20, Tanemura discloses a sensing method, comprising (Figs. 1, 2, 3A-B, and 4A, method performed by system 100): sending and receiving a plurality of first detection signals by a plurality of first transceiver channels, and the plurality of first detection signals being independent of each other ([0027, 0037, 0039-0040, 0063-0066], Fig. 4A, first mode of operation is absolute or self capacitance sensing techniques with first transceiver capacitors Tx as channels being independent of each other); sending and receiving a plurality of second detection signals by a plurality of second transceiver channels, and the plurality of second detection signals being independent of each other, wherein the plurality of first transceiver channels and the plurality of second transceiver channels are alternately arranged to form an array ([0028, 0037, 0041-0044, 0063-0066], Fig. 4A, second transceiver capacitors Rx or channels are independent of each other and arranged in a checkerboard pattern with the Tx transmitters or channels during self capacitance scan of the pixels which sends and receives a plurality of second detection signals); during a self-capacitance mode, outputting and receiving a corresponding one or a plurality of self-capacitance sensing signals by each of the plurality of first transceiver channels and the plurality of second transceiver channels ([0027, 0037, 0039-0040, 0063-0066], Fig. 4A, first mode of operation is absolute or self capacitance sensing techniques with first transceiver capacitors Tx as first transceiver channels and second transceiver electrodes Rx as second transceiver channels scanning all pixels 205 to output and receive self capacitance signals); and during a mutual-capacitance mode, outputting a plurality of mutual-capacitance sensing signals by the plurality of first transceiver channels, and receiving the plurality of mutual-capacitance sensing signals by the plurality of second transceiver channels ([0028, 0037, 0041-0044, 0063-0066], Fig. 4A, second transceiver capacitors Rx as second channels are independent of each other and arranged in a checkerboard pattern with the Tx transmitters as first channels to receive driving signals therefrom during the mutual capacitance sensing mode from driven Tx transmitters). outputting and receiving the corresponding one of the plurality of self- capacitance sensing signals by using the first transceiver channels and the second transceiver channels during the self-capacitance mode and the first transceiver channels and the second transceiver channels respectively output and receive the mutual-capacitance sensing signals in the mutual-capacitance mode ([0027, 0037, 0039-0040, 0063-0066], Fig. 4A, first mode of operation is absolute or self capacitance sensing techniques with each of the first transceiver capacitors Tx as first transceiver channels and second transceiver electrodes Rx as second transceiver channels scanning all pixels 205 to output and receive self capacitance signals; [0028, 0037, 0041-0044, 0063-0066], Fig. 4A, second mode of operation has second transceiver capacitors Rx as second channels that are independent of each other and arranged in a checkerboard pattern with the Tx transmitters as first transceiver channels, [0028], the second transceiver channels Rx respectively output and receive the mutual-capacitance sensing signals in the mutual-capacitance mode when dedicated to be both transmitters and receivers), Tanemura does not explicitly disclose determining a touch signal as a signal triggered by a finger if both the plurality of self-capacitance sensing signals and the plurality of mutual-capacitance sensing signals are received from the array, Cheng discloses using self capacitance detection and mutual capacitance detection to confirm that a user is using a finger for a capacitive touch panel (Machine translation, page 1, last paragraph). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Tanemura to have a touch signal is determined as a signal triggered by a finger if both the plurality of self-capacitance sensing signals and the plurality of mutual-capacitance sensing signals are received by the array, such as taught by Cheng, for the purpose of confirming a finger touch (Cheng, Machine translation, page 1, last paragraph). Tanemura as modified by Cheng does not explicitly disclose the touch signal is determined as a noise signal or a deformation-triggered signal if only the plurality of self-capacitance sensing signals are received from the array; and wherein a deformation-triggered signal is resulted from a judgment of a change in an air gap between panels, and the presence of the deformation-triggered signal indicates the noise signal. Lee teaches using only self capacitance sense signals received from an array to detect noise (Col. 14, lines 9-19). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Tanemura as modified by Cheng to have the touch signal is determined as a noise signal if only the plurality of self-capacitance sensing signals are received from the array, such as taught by Lee, for the purpose of detecting noise from a touch signal which can be eliminated as a baseline from a touch signal. Since Lee teaches the noise signal and the claim limitation “a deformation-triggered signal is resulted from a judgment of a change in an air gap between panels, and the presence of the deformation-triggered signal indicates the noise signal” is not further limiting when a noise signal is selected as a claim limitation due to the “or”, the Examiner considers this limitation optional). Tanemura as modified by Cheng and Lee does not explicitly disclose calibrating the touch signal when the noise signal is determined. KR ‘718 teaches wherein if the touch signal is determined as the noise signal, the touch signal is calibrated (Machine translation, page 15, 6th paragraph, at step 830, a calibrated touch input signal is determined based on removing a noise signal from the touch input signal). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Tanemura as modified by Cheng and Lee to calibrate the touch signal when the noise signal is determined, such as taught by KR ‘718, for the purpose of more accurately verifying information on a touch input by reducing noise (KR ‘718, Machine translation page 3, lines 15-16).
Conclusion
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JOSEPH PATRICK FOX
Examiner
Art Unit 2622
/JOSEPH P FOX/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622