Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-12 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence In regard to this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Petkov et al. (“Petkov”) (US No. 10,558,580) in view of Gangsto et al. (“Gangsto”) (US No. 8,143,860)
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Gangsto and Petkov references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1, Petkow discloses Figure 1: a device comprising a first circuit and a second circuit substantially as claimed: a peripheral device 104 ("first circuit") comprising an embedded processor 124 (“a processor”) (see col. 6:14-37), and a host processor 102 (“a second circuit”), coupled to the first circuit via physical bus interface 106 (see col. 5:32-6:55), the host processor 102 comprising a non-volatile bulk storage memory 112 (“a memory of non-volatile type”) that stores the peripheral device's firmware (see col. 7:15-35: “the host 102 also stores the peripheral device's firmware in bulk memory”), and configured to initialize the processor of the first circuit - Pektow discloses that the host “loads the first firmware host driver and the primary firmware image into the execution memory of the peripheral processor and then releases the peripheral processor from reset” (see col. 8:6-62), and that the peripheral processor “is held in reset when first powered on” until so released (see col. 10:39-65) - i.e., the second circuit “initializes” the processor of the first circuit exactly as claimed.
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Pektow does not expressly disclose (i) a rechargeable battery, (ii) a voltage comparator within the first circuit that compares the battery voltage to a limiting voltage, or (iii) that the second circuit's initialization of the first circuit's processor is performed specifically “if the voltage of the rechargeable battery is higher than the limiting voltage.” Gangsto remedies each of these deficiencies. Gangsto discloses a device powered by “rechargeable battery cells” (Background/Summary), including a processor - CPU 116 - and, within battery protection circuitry 106, an under-voltage comparator: “The deep under-voltage protection ensures that the battery cells will not be discharged deeper than the programmable deep under-voltage detection level. If the voltage at the VFET pin is below this level for a time longer than the programmable delay time, the FETs are automatically switched off” (see col. 10:47-63), the comparison being performed by “an accurate, programmable on-chip voltage reference by an analog comparator” (Discharge Over-Current Protection discussion). Gangsto's “deep under-voltage detection level” thus discloses the claimed “limiting voltage,” and Gangsto's comparator discloses the claimed “voltage comparator configured to compare a voltage of the rechargeable battery with a limiting voltage.”
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It would have been obvious to a POSITA, at the time of filing, to modify Pektov’s host-initiated firmware-loading/reset-release sequence (col. 10:39-65) so that the host (second circuit) performs that initialization only when a battery-voltage comparator of the type taught by Gangsto indicates that the battery voltage exceeds the applicable limiting/under-voltage threshold, rather than initializing unconditionally. The motivation to do so is expressly supplied by Gangsto itself, which teaches that a battery-powered processor system should be protected from operating - and, in Gangsto's implementation, is affirmatively powered off - when battery voltage falls below the deep under-voltage level, “giv[ing] the CPU 116 a chance to take necessary actions before the power is switched off” (Deep Under-Voltage Protection discussion, referencing col. 10:47-63). A POSITA implementing Petkov's two-chip, battery-powered host/peripheral architecture would have recognized the same risk - that loading and executing firmware on peripheral processor 104 while the shared battery is inadequately charged risks a corrupted or incomplete initialization, or unreliable subsequent operation - and would have been motivated to gate Petkov's existing reset-release/initialization step on Gangsto's battery-voltage-comparator output for exactly the reason Gangsto articulates. This is a combination of known prior-art elements (a known voltage-supervisory gating technique and a known host-to-peripheral firmware-initialization architecture) according to their established functions, producing the predictable result recited in claim 1, with a reasonable expectation of success and no showing of unexpected results. KSR, 550 U.S. at 416; MPEP § 2143(A), (G).
In regard to claim 2, further requires that “the memory of the second circuit is a flash-type memory.” Petkov’s host bulk storage memory 112 is described only generically as “non-volatile storage”/“bulk memory” (see col. 7:15-35) without specifying the underlying memory technology. Gangsto, however, discloses that flash memory was, at the time, the conventional non-volatile memory technology for storing reprogrammable boot/program code that initializes a processor, disclosing an “on-chip Flash memory 130” that “allows the program memory to be reprogrammed in-system, by a conventional non-volatile memory programmer or by an on-chip boot program running on the CPU 116” (FIG. 1 discussion), i.e., flash memory used for materially the identical purpose - storing code used to initialize/program a processor - as Petkov's bulk memory 112. It would have been obvious to a POSITA to implement Petkov's host non-volatile bulk memory 112 specifically as flash memory, this being nothing more than the use of a known memory technology (flash) for its known, conventional purpose (storing reprogrammable firmware/boot code loaded to initialize a processor), as evidenced by Petkov's own use of flash for that purpose, yielding a predictable result.
In regard to claim 3, further requires “a voltage regulator configured to supply the first and second circuits with voltage.” Gangsto discloses: “The microcontroller 100 is powered from the battery through the internal voltage regulator 102. The input to the regulator 102 is allowed to vary from 4 to 25 volts. This voltage is regulated down to 3.3V internally, which is a suitable level for the internal logic, low voltage I/O lines, and analog circuitry” (see col. 4), i.e., a single battery-derived voltage regulator supplying the on-chip logic circuitry. In the combined Gangsto/Petkov system, both the host (second circuit, Petkov's element 102) and the peripheral (first circuit, Petkov's element 104) reside in a single battery-powered handset (Petkov, background discussion of a mobile handset architecture) and would conventionally share a common battery and power-management/regulation stage. It would have been obvious to a POSITA to supply both the host and peripheral circuits of the combined system from a common battery-derived voltage regulator of the type Gangsto discloses (see col. 4), this being a routine, conventional way of powering multiple co-located integrated circuits from a single shared battery in a portable electronic device, and yielding nothing more than the predictable result of a shared, regulated supply rail.
In regard to claim 4, further requires that “the first circuit comprises a connection terminal coupled to a connection terminal of the second circuit, a signal present at the connection terminal of the first circuit being either in a first state or in a second state, according to a charge level of the rechargeable battery.” Petkov discloses a connection terminal of the first circuit (peripheral processor 104) coupled to a connection terminal of the second circuit (host processor 102) via physical bus interface 106 (see col. 5:32-6:55), across which a reset/initialization-related signal is exchanged - peripheral processor 104 is “held in reset when first powered on” and is later “released … from reset” by the host (see col. 10:39-65), i.e., the interface/terminal condition toggles between (i) a reset/not-yet-initialized state and (ii) a released/initialized state. As explained above with respect to claim 1, a POSITA combining Petkov with Gangsto’s battery-voltage-comparator-based gating (Gangsto, see col. 7-8; DUVIF discussion referencing col. 10:47-63) would have made the terminal signal's state a function of the charge-level determination made by Gangsto's comparator - a first (released/initialized) state when the battery voltage exceeds the limiting voltage, and a second (reset/held) state otherwise - for the same reasons and motivation to combine articulated above.
In regard to claim 5, further requires that “the signal present at the connection terminal of the first circuit is in the second state if the voltage of the rechargeable battery is lower than the limiting voltage.” This follows directly from Gangsto's teaching that when “the voltage at the VFET pin is below [the deep under-voltage detection] level for a time longer than the programmable delay time, the FETs are automatically switched off” (see col. 10:47-63) and the microcontroller enters power-off/protective mode, combined, for the reasons given above with respect to claim 4, with Petkov's teaching that the peripheral processor is held in a reset (not-initialized) condition absent an affirmative release (see col. 10:39-65). In the combined system, the connection-terminal signal accordingly assumes the second (reset/not-initialized) state precisely when the battery voltage is below Gangsto's limiting/under-voltage threshold, as claimed.
In regard to claim 6, further requires that “the second circuit is configured to reset the processor or to generate an alert signal if the signal present at the connection terminal of the first circuit is in the second state.” Gangsto expressly discloses generating an alert responsive to inadequate battery voltage: “The activation of a protection also issues an interrupt to the CPU 116 … A deep under-voltage early warning interrupt flag (DUVIF) within the battery protection interrupt register will be set 250 ms before the microcontroller enters power-off” (see col. 10:47-63) - an alert signal generated in response to insufficient battery voltage - in addition to the protective power-off response of col. 5-6. Petkov, in turn, discloses that the host is the entity that resets the first circuit's processor: peripheral processor 104 is “put into a reset condition by the host (so-called ‘soft reset’)” and “held in reset when first powered on” (see col. 8). Combining these teachings, as motivated above with respect to claim 1, discloses a second circuit (Petkov's host 102, modified per Gangsto's battery-voltage gating) that either resets the first circuit's processor (per Petkov, see col. 8) or generates an alert signal (per Gangsto's DUVIF interrupt, see col. 10:47-63) when the connection-terminal signal is in the second (low-battery) state, exactly as claimed - claim 6 requires only one of these two alternatives (“reset … or … generate an alert signal”), and both are independently taught.
In regard to claim 7, further requires that “a voltage of the connection terminal of the first circuit in the first state is higher than the voltage of the connection terminal of the first circuit in the second state.” This recites nothing more than the ordinary and well-understood convention of digital-logic signaling - a logic-“high”/asserted (“good”/“first”) state corresponds to a higher voltage level than a logic-“low”/de-asserted (“fault”/“second”) state - a fact so well known and routine in electronic circuit design that Examiner takes Official Notice of it under MPEP § 2144.03. This is independently evidenced by EP 1 126 352 A1, which discloses an analogous power-supervisory output signal (NPOR) that “will switch to a logic low state (when VP is less than VTP) … and will switch to a logic high state (when VP is greater than VTP)” - confirming that the higher-voltage/adequate-supply condition is conventionally represented by the logic-high state and the lower-voltage/inadequate-supply condition by the logic-low state, precisely the relationship recited in claim 7. Applying this conventional relationship to the first/second-state connection-terminal signal discussed above with respect to claims 4-6 (Petkov’s reset/release signal, gated per Gangsto's comparator) renders claim 7 obvious; no more than ordinary skill and common sense are required to arrive at the claimed voltage relationship. See KSR, 550 U.S. at 418 (a court/examiner “can take account of the inferences and creative steps that a person of ordinary skill in the art would employ”).
In regard to claim 8, further requires that “the first circuit further comprises an analog-to-digital converter configured to generate a digital value representative of the voltage of the rechargeable battery.” Gangsto discloses this limitation directly within the first-circuit mapping: “two ADCs 110 and 114 with on-chip voltage reference 112,” the voltage ADC 110 comprising “a plurality of differential channels, an input multiplexer 502 for receiving differential channels, a 12 bit sigma delta ADC 504,” wherein “the analog to digital converter input channels can measure battery cell voltages” (see Summary of Invention; Voltage ADC 110 discussion). Gangsto's voltage ADC 110 thus discloses an analog-to-digital converter, within the same on-chip circuitry mapped to claim 1's first circuit, configured to generate a digital value representative of the rechargeable battery's voltage, satisfying claim 8 without further modification of the base combination.
In regard to claim 9, further requires that “the rechargeable battery is a lithium battery.” Gangsto discloses “rechargeable battery cells” generically (Background/Summary) without expressly naming lithium chemistry in the ’860 patent itself. However, lithium-ion (Li-ion) chemistry was, at the time of filing, the predominant rechargeable battery chemistry used in the class of portable/rechargeable-battery-powered electronic devices to which Gangsto's battery-protection microcontroller is directed, of which Examiner takes Official Notice under MPEP § 2144.03. This is independently evidenced by Petkov's own related, commonly-assigned patent and product literature, which expressly describes Gangsto's battery-protection circuitry as directed to “protection circuits for Lithium Ion battery packs” and states that such inventions “help enable multi-module Lithium Ion battery packs to maximize energy storage and battery life” (see Gangsto press release, “Key Battery Pack Protection Patent Granted to Gangsto,” GlobeNewswire, Mar. 6, 2019), confirming that Gangsto's battery-protection ICs, of the type disclosed in the ’860 patent, are designed for and marketed together with lithium-ion rechargeable battery packs. It would therefore have been obvious to a POSITA to employ a lithium (Li-ion) rechargeable battery as Gangsto's “rechargeable battery cells,” this being nothing more than the use of a known, predominant battery chemistry for its known and expected purpose.
In regard to claim 10, recites the corresponding method - “comparing, by a first circuit, of a voltage of a rechargeable battery with a limiting voltage” and “initializing a processor of the first circuit, by a second circuit comprising a memory of non-volatile type, if the voltage of the rechargeable battery is higher than the limiting voltage” - and is rejected for the same reasons: the comparing step corresponds to Gangsto's battery-protection comparator function (see col. 18:5-10), and the initializing step corresponds to Petkov's host-driven firmware-loading/reset-release sequence (see col. 10:39-65) as modified per the above combination and motivation.
In regard to claim 11, further requires, “prior to the running of a program by the processor, the comparison of the voltage of the rechargeable battery with a threshold voltage, and the running of the program only if the voltage of the rechargeable battery is higher than the threshold voltage.” Gangsto's battery-protection circuitry continuously compares the battery voltage to the programmable deep under-voltage detection level and, “if the voltage at the VFET pin is below this level for a time longer than the programmable delay time, the FETs are automatically switched off” (see col. 10:47-63), preventing continued/normal operation while inadequately charged; Gangsto further discloses giving “the CPU 116 a chance to take necessary actions before the power is switched off” via the early-warning interrupt (see col. 10:47-63), evidencing that program execution is conditioned on the outcome of the voltage comparison. Petkov discloses that the host processor initiates execution on the peripheral only upon completion of firmware loading and release from reset (see col. 8). Combining these teachings for the reasons articulated above with respect to claim 1, a POSITA would have found it obvious to further condition Petkov's host-initiated “run program” command - consistent with Gangsto's own teaching of gating operation on adequate battery voltage - on the battery voltage first being confirmed, via the comparator, to exceed the applicable (threshold) voltage immediately before the host commands the peripheral processor to run the loaded program, so that the program runs only if the battery voltage is higher than the threshold voltage, as claimed.
In regard to claim 12, recites the method-claim counterpart of claim 6 - “resetting of the processor or a emission of an alert signal by the second circuit if the voltage of the rechargeable battery is lower than the limiting voltage” - and is rejected for the same reasons and evidentiary support set forth above with respect to claim 6 (see Petkov, col. 8 (host resets/holds peripheral processor in reset); Gangsto, see col. 10:47-63 (DUVIF alert interrupt to CPU 116) and see col. 10:47-67 (protective response when voltage is below the limiting/under-voltage level)).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
If Applicant traverses any statement of Official Notice set forth above, documentary evidence will be provided in the next Office Action (MPEP § 2144.03(C)).
Conclusion
All claims are rejected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
US 5,606,511 A (Microchip Technology) - "Microcontroller with brownout detection" - Discloses a microcontroller with an integrated dual-comparator brown-out detection circuit that resets the CPU when supply voltage falls below a reference, including hysteresis trip points (V1 > Vbo > V2); relevant to claim 1's comparator/reset structure, though the patent expressly disclaims battery-driven applications.
US 8,253,453 B2 - "Brown-out detection circuit" -Discloses a brown-out detection circuit generating a two-state output signal based on comparison of supply voltage to a threshold; potentially relevant to claims 4–7.
US 6,894,544 B2 - "Brown-out detector" - Discloses a PTAT/CTAT-reference-based brown-out detector producing a logic-HIGH output when supply voltage exceeds a threshold; relevant evidentiary reference for claim 7's voltage-state convention.
EP 1 126 352 A1 - "Bandgap voltage comparator used as a low voltage detector" -Discloses an on-chip bandgap-referenced low-voltage detector (NPOR) producing power-on-reset/brown-out-reset outputs with defined logic-high/logic-low behavior tied to a voltage threshold; used above as evidence for claim 7 and independently relevant to claim 1.
US 2003/0142573 A1 - "Battery backed memory with low battery voltage detection" - Discloses a battery-backed memory system with a supervisory circuit (comparator) generating a reset signal (line 48) that transitions between high/low states based on battery voltage, and a separate low-power-warning interrupt to a microprocessor; relevant to claims 4–6.
US 9,214,986 B2 - "Non-volatile memory for NFC router" - Discloses a combo/NFC-router circuit and a separate secure element with non-volatile memory, and a staged initialization sequence at power-up (first phase using on-chip ROM, second phase using external non-volatile memory 35); relevant analogous two-chip architecture, though no voltage-comparator gating is disclosed.
US 8,811,896 B2 - "Non-volatile memory for contactless systems" - Discloses an NFC controller (separate IC, volatile memory) initialized from a UICC/eSE server module containing non-volatile (flash) memory over an SWP interface, and power-scavenging/low-power initialization when battery power is unavailable; relevant analogous host/coprocessor split.
US 9,886,080 B2 - "Low voltage detection and initialization for non-volatile memory systems" - Directly combines low-voltage detection with memory-system initialization; title-level relevance to claim 1's overall concept, though directed to a different (storage-controller) context - recommended for close reading before final claim scope is set.
US 7,761,653 B2 - "Flash micro-controller with shadow boot-loader SRAM" Discloses a flash-memory boot-loader state machine that automatically reads boot code from flash into SRAM buffer 154 for CPU 146 execution upon power-on-reset 164; relevant to claim 2's flash-memory limitation and general boot-loader architecture.
US 6,856,922- "System and method for battery management using host processor" - Title suggests a host-processor-based battery management architecture; recommended for review as potentially closer combinable art for claims 1, 3–6.
US 10,978,867, "Battery protection systems", Continuation-family / related Gangsto battery-protection patents; recommended review for more specific lithium-ion chemistry disclosures to strengthen claim 9's rejection if pinpoint citation is required.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
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