DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendment
2. The amendment filed on 01/21/2026 has been entered and considered by examiner.
Specification.
3. The following title is suggested: --… DISPLAY DEVICE AND METHOD OF CONROLLING CHANNELS OF SOURCE DRIVE INTEGRATED CIRCUITS THEREIN …--.
Drawings
4. The drawings are objected to because
In a second switch circuit of Fig 7: “… 620 …” should be changed into --… 630 …--.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objection
5. Claims 10, 12-14 and 16 are objected to because of the following informalities:
In line 8 of claim 10: “… the data driving circuit …” should be changed into --… wherein the data driving circuit …--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (U.S. Pub. No. US 2008/0150865 A1) in view of Jeong (KR Pub. No. KR 1020210040238 B1), and further in view of Lin (U.S. Pub. No. US 2004/0032387 A1).
As to claim 1, Choi (Figs. 4-8) teaches a display device (a liquid crystal display device 200; Fig. 4) comprising:
a display panel (a liquid crystal display device 210) having a plurality of pixels (pixels; [0025], e.g., R sub-pixels, G sub-pixels, and B sub-pixels) (Fig. 4);
a timing controller (a timing controller 290) configured to generate channel control information (data drive control signals DDC) for each channel (data line, e.g., DL1 to DLm) on the basis of a resolution of image data (RGB data) to be written to the pixels (the pixels) (it is known that the RGB data includes resolutions, which is a measure of the number of pixels in the image and a key determinant of its quality) (Fig. 4); and
a data driving circuit (a data drive circuit 220) configured to generate a data voltage corresponding to the image data and output the data voltage to channels connected to the pixels (converts the digital RGB data, which are inputted through the timing controller 290 for each horizontal line, into analog data voltages to supply to the data lines DL1 to DLm in response to data drive control signals DDC supplied from the timing controller 290 and the RGB data is correspondingly supplied to an R sub-pixel, a G sub-pixel, and a B sub-pixel which constitute one pixel, in one-on-one; [0061], lines 1-11) (Fig. 4),
wherein the data driving circuit (the data drive circuit 220) is configured to set an enabled channel as a channel to be used and a disabled channel as a channel not to be used for the channels based on the channel control information (source output enable signals SOE included in the data drive control signal DDC is used to set an enabled data line; ; and disabled data line; [0070], lines 8-11; [0077], lines 1-7) (Figs. 4-5), and
wherein the data driving circuit (the data drive circuit 220) comprises:
a shift register (a shift register 222) configured to sample bits of the image data for each channel and output the sampled bits (generate a sampling signal used in latching the data; [0074], lines 10-11) (Fig. 5);
a second switch unit (first to mth switches 228-1 to 228-m) configured to set whether the data voltage (analog data voltages) output from the data voltage generation circuit (the data drive circuit 220) is to be output to a relevant channel for each channel (relevant data line of the data lines DL1 to DLm)according to the channel control information (the data drive control signals DDC) (Fig. 4).
Choi does not expressly teach [wherein the data driving circuit comprises:] a data voltage generation circuit configured to receive the image data from the shift register and generate the data voltage for each channel; a first switch unit configured to set whether the image data is input to the data voltage generation circuit for each channel according to the channel control information.
Jeong (Figs. 1-15) teaches [wherein the data driving circuit comprises:]
a data voltage generation circuit (a second latch LAT2, a digital to analog converter DAC, and an output buffer BUF) configured to receive the image data from the shift register (receive the pixel data stored in the first latch LAT1, which is supplied from the shift register SR; page 8, par. 4, line 1 and page 8, par. 5, line 3) and generate the data voltage for each channel (the DAC converts the pixel data input from the second latch LAT2 into a gamma compensation voltage to generate a data voltage; page 8, par. 12, line 1) (Fig. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used a shift register as taught by Jeong in a liquid crystal display device of Choi because the shift register eliminates flickering and image artifacts during display updates.
Choi and Jeong do not expressly teach [wherein the data driving circuit comprises:] a first switch unit configured to set whether the image data is input to the data voltage generation circuit for each channel according to the channel control information.
Lin (Fig. 2) teaches [wherein the data driving circuit comprises:]
a first switch unit (data switches C1 to Cn) configured to set whether the image data (the digital image signals inputted from N data lines Din) is input to the data voltage generation circuit (N-bit latch units L1 to Ln, enabling switches E1 to En, and N-bit digital-to-analog converters D1 to Dn) for each channel (each data line) according to the channel control information (control signal to turn on/off the data switches from the data shift register 205) (Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used a plurality of data switches as taught by Lin in a liquid crystal display device of Choi as modified by Jeong because the data switches separate the process of loading new data from the process of displaying the data in order to prevent visual artifacts like flicker.
As to claim 3, Jeong teaches wherein the data voltage generation circuit (the second latch LAT2, the digital to analog converter DAC, and the output buffer BUF) comprises:
a plurality of latch circuits (the second latch LAT2) configured to convert bits of the image data into a parallel type data system (includes second switch elements SW2 respectively connected to the channels of the DAC, output pixel data in response to a pulse of the second CLT signal CLT2, and simultaneously input bits of the Nth pixel line data stored in synchronization with the rising edge of the second CLT signal CLT2 to the DAC; page 8, par. 8, lines 1-2 and page 8, par. 9, lines 1-3) (Figs. 12-14); and
a plurality of output amplifiers (input buffers BUF) configured to output a data voltage corresponding to the image data for each channel (supply a data voltage to the data line DL in response to a pulse of the SOE signal; page 8, par. 13, lines 1-3) (Figs. 12-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used latches and buffers as taught by Jeong in a liquid crystal display device of Choi as modified by Lin because latches and buffers ensures that the correct image data is held stage and then sent to the display with the necessary strength to create a bright, clear picture.
As to claim 10, this claim differs from claim 1 in that claim 1 is a display device claim whereas claim 10 is a method claim thereof. Thus, claim 10 is analyzed as previously discussed with respect to claim 1.
8. Claims 7-8 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, in view of Jeong as applied to claim 1/10 above, in view of Lin as applied to claim 1/10 above, and further in view of Do (U.S. Pub. No. US 2018/0122294 A1).
As to claim 7, Choi, Jeong, and Lin teach the display device of claim 1.
Choi, Jeong, and Lin do not expressly teach wherein the timing controller is configured to transmit the channel control information to the data driving circuit during a vertical blank period.
Do (Figs. 1-8) teaches
wherein the timing controller (the timing controller 11) is configured to transmit the channel control information to the data driving circuit (the source drive IC 12) during a vertical blank period (the timing controller 11 may transmit the control data packet during the vertical blank period; [0092], lines 5-9) (Figs. 4-7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used transmission of control data during the vertical blank period as taught by Do in a liquid crystal display device of Choi as modified by Jeong and Lin because transmission of control data during the vertical blank period provides a way to send supplementary information that does not interfere with the main image content.
As to claim 8, Choi, Jeong, and Lin teach the display device of claim 1.
Jeong also teaches
wherein the data driving circuit comprises a source drive integrated circuit (source drive ICs SIC1 to SICn) having a plurality of channels (data lines) (Fig. 2).
Choi, Jeong, and Lin do not expressly teach [wherein] the timing controller is configured to transmit the channel control information to the source drive integrated circuit through an embedded panel interface (EPI) transmission data format.
Do (Figs. 1-8) teaches
[wherein] the timing controller (the timing controller 11) is configured to transmit the channel control information (the control data packet) to the source drive integrated circuit (the source drive IC 12) through an embedded panel interface (EPI) transmission data format (two EPI wiring pair (EPI1, EPI2)) ([0092], lines 1-9) (Figs. 4-7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used an embedded panel interface (EPI) data transmission as taught by Do in a liquid crystal display device of Choi as modified by Jeong and Lin because an embedded panel interface (EPI) data transmission offers higher performance, improved power efficiency, and simpler hardware designs.
As to claims 13-14, these claims differ from claims 7-8 in that claims 7-8 are display device claims whereas claims 13-14 is method claims thereof. Thus, claims 13-14 are analyzed as previously discussed with respect to claims 7-8, respectively.
Allowable Subject Matter
9. Claims 4-6, 9, 12 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art record, Choi, Jeong, Lin and Do, either individually or in combination, does not teach a limitation “a plurality of first switches configured to output an enable signal or a disable signal to each of the plurality of latch circuits based on the channel control information” of claim 4, a limitation “wherein the EPI transmission data format includes long packet data indicating enable or disable setting information of each of the plurality of channels of the source drive integrated circuit as 1 bit” of claim 9, a limitation “outputting, by the first switch unit, an enable signal or a disable signal to each of the plurality of latch circuits based on the channel control information” of claim 12, a limitation “wherein a same channel control signal of the channel control information is input to a first switch in the first switch unit and a second switch in the second switch unit for controlling a same channel” of claim 15, and a limitation “wherein the setting an enabled channel as a channel to be used and a disabled channel as a channel not to be used for the channels according to the channel control information comprises inputting a same channel control signal of the channel control information to a first switch in the first switch unit and a second switch in the second switch unit for controlling a same channel” of claim 16 in combination with other limitations of corresponding claim, the base claim, and any intervening claims.
Response to Arguments
10. Applicants’ arguments with respect to claims 1, 3, 7-8, 10 and 13-14 have been considered but are moot in view of the new grounds of rejection.
In view of amendment, references of Choi, Jeong, Lin and Do, have been used for the new grounds of rejection.
Therefore, the Office maintains the rejections as recited above.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kwang-Su Yang whose telephone number is (571)270-7307. The examiner can normally be reached on Mon-Fri during 9:00am-6:00pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen, can be reached on (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KWANG-SU YANG/
Primary Examiner, Art Unit 2623
Prosecution Insights