Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed July 13, 2026 is acknowledged. Applicant canceled claims 14-22 directed to withdrawn inventions.
As to newly added claims 23-31, independent claims 23 and 29 do not read on the elected invention I: at least a third inverter or MOS capacitors of different types claimed in claim1 are missing in each of independent claims 23 and 29. As such, claims 23-31 are withdrawn from consideration for patentability.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0024130 to Koike.
With respect to claims 1 and 6-9, Koike discloses in Fig. 2 an integrated circuit (e.g., as discussed below), comprising:
a first pad (e.g., 13 is a pad as per Para. 37);
a first input driver (e.g., the Fig. 2 circuit) coupled to the first pad (e.g., 13); and
a first filter (e.g., C2) in the first input driver, the first filter including:
a first inverter (e.g., the inverter coupled in parallel to the resistor between N3 and N4);
a second inverter (e.g., 211) coupled in series with the first inverter;
a third inverter (e.g., an inverter coupled to receive the output of 14 as discussed below) coupled in series with the second inverter (e.g., 211);
a first MOS capacitor (e.g., C2 may be an NFET capacitor) of a first conductivity type coupled between (e.g., C2 is coupled to N4 which is between (1) the inverter coupled in parallel to the resistor between N3 and N4 and (2) 211) the first inverter (e.g., the inverter coupled in parallel to the resistor between N3 and N4) and the second inverter (e.g., 211); and
a second MOS capacitor (e.g., C12 may be a PFET capacitor) of a second conductivity type coupled between the second inverter and the third inverter. Koike fails to disclose that (1) an inverter is coupled to the output of 14 to invert the output, (2) C2 coupled to ground and C12 coupled to a power supply may be formed of an NFET capacitor and a PFET capacitor, respectively, and (3) the Fig. 2 circuit may be integrated to save space/costs. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that (1) an inverter may be used at an output to invert the output, (2) a capacitor coupled to ground and a capacitor coupled to a power supply may be formed of an NFET capacitor coupled to ground at drain/source/body nodes and a PFET capacitor coupled to a power supply at drain/source/body nodes, respectively, and (3) a circuit may be integrated to save space/costs; an official notice of the foregoing fact is hereby taken. For example, US 2008/0224745 to Lin discloses in Fig. 3 a PMOS capacitor coupled to a power supply at the drain/source/body nodes and an NMOS capacitor coupled to ground at the drain/source nodes. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the Fig. 2 circuit of Koike to (1) add an inverter at the output of 14 by using the notoriously well-known method of adding an inverter to an output to invert the output because such a modification allows an inversion for for applications needing an inverted output, (2) form C2 coupled to ground and C12 coupled to a power supply in Fig. 2 of Koike by using the notoriously well-known method of implementing a capacitor coupled to ground and a capacitor coupled to a power supply with an NFET capacitor coupled to ground at drain/source/body nodes and a PFET capacitor coupled to a power supply at drain/source/body nodes, respectively, because C2 coupled to ground and C12 coupled to a power supply in Fig. 2 of Koike require a specific implementation in fabrication and the notoriously well-known method provides such a specific method, and (3) implement the Fig. 2 circuit of Koike by using the notoriously well-known method of integrating a circuit because such a modification saves space/costs.
Allowable Subject Matter
Claims 2-5 and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUNG KIM/
Primary Examiner, Art Unit 2836
Prosecution Insights