DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 are present for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/18/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12 and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2025/0078713).
RE claim 12, Lee discloses that a display device (see figure and section [0046]; i.e., display device 100), comprising: a first pixel connected to a first scan line, a data line, a first power line to which a first power voltage is supplied, and a second power line to which a second power voltage is suppled (see figures 1&2&8 and sections [0047], [0048], [0067], [0072]; i.e., first pixel PXL connected first scan line SCL, a data line DL, a first power line VDD/PL1 to which a first power voltage is supplied, and a second power line VSS/PL2 to which a second power voltage is suppled), a second pixel connected to a second scan line, the data line, the first power line, and the second power line (see figures 1&8 and sections [0116], [0117], [0120]; i.e., a second pixel PXL_1 connected to a second scan line SCL1, the data line DL, the first power line VDD/PL1 and the second power line VSS/PL2); a gate driving circuit configured to supply a first scan signal and a second scan signal to the first scan line and the second scan line, respectively (see figure 1 and section [0047], [0052], [0053]; i.e., the gate driver 120 to supply a first scan signal to first scan line SCL and a second scan signal to second scan line SSL, respectively); and a data driver configured to supply a data signal to the data line (see figure 1 and sections [0047], [0055]; i.e., data driver 130 to supply a data signal to the data line DL), wherein in a period in which any one of the first scan signal and the second scan signal has a turn-on level, the other one of the first scan signal and the second scan signal has a turn-off level (see section [0126]; i.e., in the first period P1, after the first scan signal SC1 is changed to a turn-off voltage level, the second scan signal SC2 may have the turn-on voltage level).
RE claim 13, Lee discloses that wherein in a first mode including a period in which the first scan signal has the turn-on level, the data signal is supplied to the first pixel so that the first pixel emits light (see sections [0057], [0006], [0063], [0064]; i.e., in a separate mode or sensing period, wherein the pixel is configured to emit light during the first period based on the first data signal, and to emit light during the second period based on the second data signal), and wherein in a second mode including a period in which the second scan signal has the turn-on level, the data signal is supplied to the second pixel so that the second pixel emit light (see sections [0017], [0006], [0057], [0081]; i.e., the pixel is configured to emit light during the first period based on the first data signal, and to emit light during the second period based on the second data signal).
Allowable Subject Matter
Claims 1-11 are allowable over the prior art of record because none of the prior art of record teaches or fairly suggests the limitation of that, an output unit configured to output a first scan signal and a second scan signal based on a first selection scan signal, a first clock signal, and a control signal, wherein the output unit includes: a second controller configured to control a voltage of the first output node and a voltage of the second output node, output the voltage of the first output node as the first scan signal, and output the voltage of the second output node as the second scan signal, based on the first clock signal, a first voltage, and a second voltage being lower than the first voltage, in the environment of claim 1. The closest prior art of record is Lee (US 2022/0366836). Lee (US 2022/0366836) teaches that a scan driver including a plurality of stages, wherein a n-th stage among the plurality of stages comprising a first input unit controlling a voltage of a first node in response to a previous carry signal, a scan output unit outputting a current scan signal corresponding to a scan clock signal in response to the voltage of the first node, a first switching unit controlling a voltage of a second node in response to the previous carry signal, a sensing output unit outputting a current sensing signal corresponding to a sensing clock signal in response to the voltage of the second node, a carry output unit outputting a current carry signal corresponding to a carry clock signal in response to the voltage of the second node, and a second switching unit controlling the voltage of the second node in response to the sensing clock signal or the carry clock signal.
Claims 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 14-17 are allowable because none of the prior art of record teaches or fairly suggests the limitation of that, a second driving transistor connected between the first power line and a sixth node and configured to generate a second driving current flowing from the first power line to the second power line via the second light emitting diode, in the environment of claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zou et al (US 2021/0366352)
Shin et al (US 2025/0201158)
Jeong et al (US 2026/0011285)
Any inquiry concerning this communication from the examiner should be directed to FRED TZENG whose telephone number is 571-272-7565. The examiner can normally be reached on weekdays from 2:0 pm to 10:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached on 571-272-0666. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300 for regular communications and 571-273-7565 for After Final communications.
Informal regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docs for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000 (IN USA).
/FRED TZENG/ Primary Examiner, Art Unit 2625
FFT
January 12, 2026